35 lines
1.2 KiB
Diff
35 lines
1.2 KiB
Diff
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From: =?utf-8?q?Kamil_Trzci=C5=84ski?= <ayufan@ayufan.eu>
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Date: Fri, 8 Jan 2021 00:19:23 +0100
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Subject: [PATCH 02/36] drm: dw-mipi-dsi-rockchip: Ensure that lane is
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properly configured
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MIME-Version: 1.0
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Content-Type: text/plain; charset="utf-8"
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Content-Transfer-Encoding: 8bit
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???
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Signed-of-by: Kamil Trzciński <ayufan@ayufan.eu>
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---
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drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c | 8 ++++++++
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1 file changed, 8 insertions(+)
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diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
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index a9acbcc..53c8b40 100644
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--- a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
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+++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
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@@ -406,6 +406,14 @@ static int dw_mipi_dsi_phy_init(void *priv_data)
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*/
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vco = (dsi->lane_mbps < 200) ? 0 : (dsi->lane_mbps + 100) / 200;
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+ if (dsi->cdata->lanecfg1_grf_reg) {
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+ regmap_write(dsi->grf_regmap, dsi->cdata->lanecfg1_grf_reg,
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+ dsi->cdata->lanecfg1);
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+
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+ dev_info(dsi->dev, "dw_mipi_dsi_phy_init / dw_mipi_dsi_rockchip_config: %08x => set=%08x\n",
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+ dsi->cdata->lanecfg1_grf_reg, dsi->cdata->lanecfg1);
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+ }
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+
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i = max_mbps_to_parameter(dsi->lane_mbps);
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if (i < 0) {
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DRM_DEV_ERROR(dsi->dev,
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