gjdwebserver-overlay/sys-kernel/pinephone-sources/files/improve-jack-button-handling-and-mic.patch

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2021-12-03 10:03:17 +01:00
From cdbf7ca5c0e1f2aa390458949713931116e0a060 Mon Sep 17 00:00:00 2001
From: Ondrej Jirman
Date: Wed, 12 May 2021 21:37:03 +0200
Subject: ASoC: sunxi: sun8i-codec: Improve jack button handling and mic
detection
Setup ADC so that it samples with period of 16ms, disable smoothing
and enable MDATA threshold (should be below idle voltage/HMIC_DATA
value). Also enable HMIC_N, which makes sure we get HMIC_N samples
after HMIC_DATA crosses the threshold.
This allows us to perform steady state detection of HMIC_DATA, by
comparing current and previous ADC samples, to detect end of the
transient when the user de-presses the button. Otherwise ADC could
sample anywhere within the transient, and the driver may mis-issue
key-press events for other buttons attached to the resistor ladder.
Signed-off-by: Ondrej Jirman <megous@megous.com>
---
sound/soc/sunxi/sun50i-codec-analog.c | 12 ++
sound/soc/sunxi/sun8i-codec.c | 241 +++++++++++++++++++++++++---------
2 files changed, 188 insertions(+), 65 deletions(-)
diff --git a/sound/soc/sunxi/sun50i-codec-analog.c b/sound/soc/sunxi/sun50i-codec-analog.c
index b5de3cbd2062..fcef3aafd0ca 100644
--- a/sound/soc/sunxi/sun50i-codec-analog.c
+++ b/sound/soc/sunxi/sun50i-codec-analog.c
@@ -116,6 +116,11 @@
#define SUN50I_ADDA_HS_MBIAS_CTRL 0x0e
#define SUN50I_ADDA_HS_MBIAS_CTRL_MMICBIASEN 7
+#define SUN50I_ADDA_MDET_CTRL 0x1c
+#define SUN50I_ADDA_MDET_CTRL_SELDETADC_FS 4
+#define SUN50I_ADDA_MDET_CTRL_SELDETADC_DB 2
+#define SUN50I_ADDA_MDET_CTRL_SELDETADC_BF 0
+
#define SUN50I_ADDA_JACK_MIC_CTRL 0x1d
#define SUN50I_ADDA_JACK_MIC_CTRL_JACKDETEN 7
#define SUN50I_ADDA_JACK_MIC_CTRL_INNERRESEN 6
@@ -501,6 +506,13 @@ static int sun50i_a64_codec_probe(struct snd_soc_component *component)
codec->internal_bias_resistor <<
SUN50I_ADDA_JACK_MIC_CTRL_INNERRESEN);
+ /* Select sample interval of the ADC sample to 32ms */
+ regmap_update_bits(component->regmap, SUN50I_ADDA_MDET_CTRL,
+ 0x7 << SUN50I_ADDA_MDET_CTRL_SELDETADC_FS |
+ 0x3 << SUN50I_ADDA_MDET_CTRL_SELDETADC_BF,
+ 0x3 << SUN50I_ADDA_MDET_CTRL_SELDETADC_FS |
+ 0x3 << SUN50I_ADDA_MDET_CTRL_SELDETADC_BF);
+
return 0;
}
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