gjdwebserver-overlay/sys-kernel/pinephone-sources/files/0059-arm64-dts-rk3399-pinephone-pro-Use-DCLK_VOP-_FRAC-to.patch

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2022-01-10 13:52:54 +01:00
From: Ondrej Jirman <megous@megous.com>
Date: Mon, 15 Nov 2021 23:52:40 +0100
Subject: [PATCH 16/18] arm64: dts: rk3399-pinephone-pro: Use DCLK_VOP*_FRAC
to achieve precise rates
By setting parents of DCLK_VOP1_DIV to frac/cpll we can achieve
various clock rates needed by display engine precisely.
Signed-off-by: Ondrej Jirman <megous@megous.com>
---
arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts b/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts
index f6eac416..4603788 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts
@@ -1211,6 +1211,9 @@ &usbdrd_dwc3_0 {
&vopb {
status = "okay";
+ assigned-clocks = <&cru DCLK_VOP0_DIV>, <&cru DCLK_VOP0>, <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
+ assigned-clock-rates = <0>, <0>, <400000000>, <100000000>;
+ assigned-clock-parents = <&cru PLL_CPLL>, <&cru DCLK_VOP0_FRAC>;
};
&vopb_mmu {
@@ -1219,6 +1222,9 @@ &vopb_mmu {
&vopl {
status = "okay";
+ assigned-clocks = <&cru DCLK_VOP1_DIV>, <&cru DCLK_VOP1>, <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
+ assigned-clock-rates = <0>, <0>, <400000000>, <100000000>;
+ assigned-clock-parents = <&cru PLL_CPLL>, <&cru DCLK_VOP1_FRAC>;
};
&vopl_mmu {