38 lines
1.3 KiB
Diff
38 lines
1.3 KiB
Diff
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From: Ondrej Jirman <megous@megous.com>
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Date: Mon, 15 Nov 2021 23:52:40 +0100
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Subject: [PATCH 16/18] arm64: dts: rk3399-pinephone-pro: Use DCLK_VOP*_FRAC
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to achieve precise rates
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By setting parents of DCLK_VOP1_DIV to frac/cpll we can achieve
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various clock rates needed by display engine precisely.
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Signed-off-by: Ondrej Jirman <megous@megous.com>
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---
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arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts | 6 ++++++
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1 file changed, 6 insertions(+)
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diff --git a/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts b/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts
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index 69a9cd4..680eb49 100644
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--- a/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts
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+++ b/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts
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@@ -1211,6 +1211,9 @@ &usbdrd_dwc3_0 {
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&vopb {
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status = "okay";
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+ assigned-clocks = <&cru DCLK_VOP0_DIV>, <&cru DCLK_VOP0>, <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
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+ assigned-clock-rates = <0>, <0>, <400000000>, <100000000>;
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+ assigned-clock-parents = <&cru PLL_CPLL>, <&cru DCLK_VOP0_FRAC>;
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};
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&vopb_mmu {
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@@ -1219,6 +1222,9 @@ &vopb_mmu {
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&vopl {
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status = "okay";
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+ assigned-clocks = <&cru DCLK_VOP1_DIV>, <&cru DCLK_VOP1>, <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
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+ assigned-clock-rates = <0>, <0>, <400000000>, <100000000>;
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+ assigned-clock-parents = <&cru PLL_CPLL>, <&cru DCLK_VOP1_FRAC>;
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};
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&vopl_mmu {
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