diff --git a/dev-embedded/u-boot-pinephone-pro/Manifest b/dev-embedded/u-boot-pinephone-pro/Manifest index 98ca293..3a1d2f8 100644 --- a/dev-embedded/u-boot-pinephone-pro/Manifest +++ b/dev-embedded/u-boot-pinephone-pro/Manifest @@ -1,2 +1,3 @@ -DIST trusted-firmware-a-2.6.tar.gz 6007293 BLAKE2B 860efad37acab15478b725692ebd3ae88205b0048869cc5f3381a465646f789f929480d04552d7b26b31672e636651a00378c41a77f275acaff73ee6a3eedbab SHA512 bfd7df42abd51907264359463c5ab483fc82241fce9344df51dd89e6a65fc8a5c5b3c1481830c60dede8356326bd25f66516d623fda5bc2a9913000b8865ab37 -DIST u-boot-2022.04.tar.gz 22791864 BLAKE2B 20c96c6035c8dd6b3aae985064231d48ce02feddf9f392f022a94cb82525ea93f5467f38afebf5733e095b7b0a3ad9142c25b543f4172eb334802f128e0db867 SHA512 41d86f0196c85cde4e96372e658d13ffc4caf3903a46ab52c7823d9444c246860a288e9d6b66cbdace092e749b3bc99514e1c82d2a59a2642db748f0880894bf +DIST trusted-firmware-a-2.7.0.tar.gz 6511871 BLAKE2B d27be086274382bce273f3d9a04840b31577a757cfbc0cf6e767668d43177d17b392893b8fa1ddcd033312b7e39924a0997220c852fb3e1f12ed386ebc7d666a SHA512 28e46a25f0cb6de8338ad9766aa66b36df6cee2f1e732bce0cb9efcaf5f0d360a38e5ccacbfefe9b875e3ce07e825a9b2632609af48956267d10509ecfee85f6 +DIST u-boot-2022.07_rc6.tar.gz 23213674 BLAKE2B 6b639702178e179d07f9fcdf5454abdaa6b3fec439d83b5c54b68870f52d809c464aa3feffc65cbe6a82872087929e89d77d0bce7ca5cec4536bef8d7321a75f SHA512 10ead59444a11f913ee05a032e0508838634a2108cd3c3ef02cd81c9dd0211295e7ffe7d331eb36062bad227c7b4413a2b4540a24bc118cf11ce5af99a9f29ea +DIST v0.5.tar.gz 189577 BLAKE2B 4248e21ad0a100b34eb470e6a3a23a68cfb973018444202e4e1dac3b89ba10b4c9673d21932069e94356533b0de7bb0f0e103a43225cca042c3b0e7936140de9 SHA512 1a3811053fd3a27285a1377888ab5b36e9363a2f5818f69966eb7f5214e571475a2a7865b9e1b68387940a9a7e9dc3841d2458544c155aecc5b9da041eb946ba diff --git a/dev-embedded/u-boot-pinephone-pro/files/.gitlab-ci.yml b/dev-embedded/u-boot-pinephone-pro/files/.gitlab-ci.yml old mode 100644 new mode 100755 diff --git a/dev-embedded/u-boot-pinephone-pro/files/1001-Correct-boot-order-to-be-USB-SD-eMMC.patch b/dev-embedded/u-boot-pinephone-pro/files/1001-Correct-boot-order-to-be-USB-SD-eMMC.patch deleted file mode 100644 index 5b218b5..0000000 --- a/dev-embedded/u-boot-pinephone-pro/files/1001-Correct-boot-order-to-be-USB-SD-eMMC.patch +++ /dev/null @@ -1,28 +0,0 @@ -From f97401137daa1cb75532c373bbcb5011f1e03585 Mon Sep 17 00:00:00 2001 -From: Dan Johansen -Date: Sun, 10 Oct 2021 20:19:02 +0200 -Subject: [PATCH] Correct boot order to be USB -> SD -> eMMC - -Signed-off-by: Dan Johansen ---- - include/configs/rockchip-common.h | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/include/configs/rockchip-common.h b/include/configs/rockchip-common.h -index ba7061a287..5dc92373b2 100644 ---- a/include/configs/rockchip-common.h -+++ b/include/configs/rockchip-common.h -@@ -55,9 +55,9 @@ - - #ifdef CONFIG_ROCKCHIP_RK3399 - #define BOOT_TARGET_DEVICES(func) \ -+ BOOT_TARGET_USB(func) \ - BOOT_TARGET_MMC(func) \ - BOOT_TARGET_NVME(func) \ -- BOOT_TARGET_USB(func) \ - BOOT_TARGET_PXE(func) \ - BOOT_TARGET_DHCP(func) \ - BOOT_TARGET_SF(func) --- -2.33.0 - diff --git a/dev-embedded/u-boot-pinephone-pro/files/1001-pinephone-Add-volume_key-environment-variable.patch b/dev-embedded/u-boot-pinephone-pro/files/1001-pinephone-Add-volume_key-environment-variable.patch new file mode 100644 index 0000000..653d6ac --- /dev/null +++ b/dev-embedded/u-boot-pinephone-pro/files/1001-pinephone-Add-volume_key-environment-variable.patch @@ -0,0 +1,177 @@ +From 0612580e68fa584d415f8080f65da2d4873664fe Mon Sep 17 00:00:00 2001 +From: Ondrej Jirman +Date: Tue, 11 Feb 2020 14:10:05 +0100 +Subject: [PATCH 23/29] pinephone: Add volume_key environment variable + +When the user has a volume key pressed volume_key variable will +contain either value 'down' or 'up', otherwise it will be empty. + +Signed-off-by: Ondrej Jirman +--- + board/sunxi/Makefile | 1 + + board/sunxi/board.c | 18 ++++++++++ + board/sunxi/lradc.c | 81 ++++++++++++++++++++++++++++++++++++++++++++ + board/sunxi/lradc.h | 11 ++++++ + 4 files changed, 111 insertions(+) + create mode 100644 board/sunxi/lradc.c + create mode 100644 board/sunxi/lradc.h + +diff --git a/board/sunxi/Makefile b/board/sunxi/Makefile +index d96b7897..a096a5c7 100644 +--- a/board/sunxi/Makefile ++++ b/board/sunxi/Makefile +@@ -12,3 +12,4 @@ obj-$(CONFIG_MACH_SUN4I) += dram_sun4i_auto.o + obj-$(CONFIG_MACH_SUN5I) += dram_sun5i_auto.o + obj-$(CONFIG_MACH_SUN7I) += dram_sun5i_auto.o + obj-$(CONFIG_CHIP_DIP_SCAN) += chip.o ++obj-$(CONFIG_MACH_SUN50I) += lradc.o +diff --git a/board/sunxi/board.c b/board/sunxi/board.c +index 2790a0f9..50344342 100644 +--- a/board/sunxi/board.c ++++ b/board/sunxi/board.c +@@ -46,6 +46,7 @@ + #include + #include + #include ++#include "lradc.h" + #include + + DECLARE_GLOBAL_DATA_PTR; +@@ -588,6 +589,12 @@ void sunxi_board_init(void) + { + int power_failed = 0; + ++#ifdef CONFIG_MACH_SUN50I ++ // we init the lradc in SPL to get the ADC started early to have ++ // a valid sample when U-Boot main binary gets executed. ++ lradc_enable(); ++#endif ++ + #ifdef CONFIG_LED_STATUS + if (IS_ENABLED(CONFIG_SPL_DRIVERS_MISC)) + status_led_init(); +@@ -861,6 +868,17 @@ int misc_init_r(void) + env_set("fdtfile", str); + } + ++#ifdef CONFIG_MACH_SUN50I ++ int key = lradc_get_pressed_key(); ++ if (key == KEY_VOLUMEDOWN) ++ env_set("volume_key", "down"); ++ else if (key == KEY_VOLUMEUP) ++ env_set("volume_key", "up"); ++ ++ // no longer needed ++ lradc_disable(); ++#endif ++ + setup_environment(gd->fdt_blob); + + return 0; +diff --git a/board/sunxi/lradc.c b/board/sunxi/lradc.c +new file mode 100644 +index 00000000..693b198e +--- /dev/null ++++ b/board/sunxi/lradc.c +@@ -0,0 +1,81 @@ ++#include ++#include ++#include "lradc.h" ++ ++#define LRADC_BASE 0x1c21800 ++ ++#define LRADC_CTRL (LRADC_BASE + 0x00) ++#define LRADC_INTC (LRADC_BASE + 0x04) ++#define LRADC_INTS (LRADC_BASE + 0x08) ++#define LRADC_DATA0 (LRADC_BASE + 0x0c) ++#define LRADC_DATA1 (LRADC_BASE + 0x10) ++ ++/* LRADC_CTRL bits */ ++#define FIRST_CONVERT_DLY(x) ((x) << 24) /* 8 bits */ ++#define CHAN_SELECT(x) ((x) << 22) /* 2 bits */ ++#define CONTINUE_TIME_SEL(x) ((x) << 16) /* 4 bits */ ++#define KEY_MODE_SEL(x) ((x) << 12) /* 2 bits */ ++#define LEVELA_B_CNT(x) ((x) << 8) /* 4 bits */ ++#define HOLD_KEY_EN(x) ((x) << 7) ++#define HOLD_EN(x) ((x) << 6) ++#define LEVELB_VOL(x) ((x) << 4) /* 2 bits */ ++#define SAMPLE_RATE(x) ((x) << 2) /* 2 bits */ ++#define ENABLE(x) ((x) << 0) ++ ++/* LRADC_INTC and LRADC_INTS bits */ ++#define CHAN1_KEYUP_IRQ BIT(12) ++#define CHAN1_ALRDY_HOLD_IRQ BIT(11) ++#define CHAN1_HOLD_IRQ BIT(10) ++#define CHAN1_KEYDOWN_IRQ BIT(9) ++#define CHAN1_DATA_IRQ BIT(8) ++#define CHAN0_KEYUP_IRQ BIT(4) ++#define CHAN0_ALRDY_HOLD_IRQ BIT(3) ++#define CHAN0_HOLD_IRQ BIT(2) ++#define CHAN0_KEYDOWN_IRQ BIT(1) ++#define CHAN0_DATA_IRQ BIT(0) ++ ++// this is for PinePhone only ++ ++int lradc_get_pressed_key(void) ++{ ++ uint32_t val; ++ uint32_t vref = 3000000 * 2 / 3; ++ ++ val = readl(LRADC_DATA0) & 0x3f; ++ val = val * vref / 63; ++ ++// printf("lradc=%u\n", val); ++ ++ if (val < 200000) // 158730 ++ return KEY_VOLUMEUP; ++ else if (val < 400000) // 349206 ++ return KEY_VOLUMEDOWN; ++ ++ return 0; ++} ++ ++void lradc_enable(void) ++{ ++ // aldo3 is always on and defaults to 3V ++ ++ writel(0xffffffff, LRADC_INTS); ++ writel(0, LRADC_INTC); ++ ++ /* ++ * Set sample time to 4 ms / 250 Hz. Wait 2 * 4 ms for key to ++ * stabilize on press, wait (1 + 1) * 4 ms for key release ++ */ ++ writel(FIRST_CONVERT_DLY(0) | LEVELA_B_CNT(0) | HOLD_EN(0) | ++ SAMPLE_RATE(0) | ENABLE(1), LRADC_CTRL); ++ ++} ++ ++void lradc_disable(void) ++{ ++ writel(0xffffffff, LRADC_INTS); ++ writel(0, LRADC_INTC); ++ ++ /* Disable lradc, leave other settings unchanged */ ++ writel(FIRST_CONVERT_DLY(2) | LEVELA_B_CNT(1) | HOLD_EN(1) | ++ SAMPLE_RATE(2), LRADC_CTRL); ++} +diff --git a/board/sunxi/lradc.h b/board/sunxi/lradc.h +new file mode 100644 +index 00000000..c908401b +--- /dev/null ++++ b/board/sunxi/lradc.h +@@ -0,0 +1,11 @@ ++#pragma once ++ ++enum { ++ KEY_NONE = 0, ++ KEY_VOLUMEDOWN = 1, ++ KEY_VOLUMEUP = 2, ++}; ++ ++int lradc_get_pressed_key(void); ++void lradc_enable(void); ++void lradc_disable(void); +-- +2.34.1 + diff --git a/dev-embedded/u-boot-pinephone-pro/files/1002-Enable-led-on-boot-to-notify-user-of-boot-status.patch b/dev-embedded/u-boot-pinephone-pro/files/1002-Enable-led-on-boot-to-notify-user-of-boot-status.patch new file mode 100644 index 0000000..85d33d7 --- /dev/null +++ b/dev-embedded/u-boot-pinephone-pro/files/1002-Enable-led-on-boot-to-notify-user-of-boot-status.patch @@ -0,0 +1,58 @@ +From bbb3d10356bcbf931a63a70610f1e7869eeebd21 Mon Sep 17 00:00:00 2001 +From: Marius Gripsgard +Date: Tue, 5 May 2020 16:51:13 +0200 +Subject: [PATCH 24/29] Enable led on boot to notify user of boot status + +--- + arch/arm/mach-sunxi/Kconfig | 5 +++++ + board/sunxi/board.c | 6 ++++++ + configs/pinephone_defconfig | 1 + + 3 files changed, 12 insertions(+) + +diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig +index b0191d0080..7a46bb4481 100644 +--- a/arch/arm/mach-sunxi/Kconfig ++++ b/arch/arm/mach-sunxi/Kconfig +@@ -1,5 +1,10 @@ + if ARCH_SUNXI + ++config PINEPHONE_LEDS ++ bool "Notify boot status via LEDs on PinePhone" ++ ---help--- ++ LED boot notification. ++ + config SPL_LDSCRIPT + default "arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" if !ARM64 + +diff --git a/board/sunxi/board.c b/board/sunxi/board.c +index 2bc9883092..59f7c2c5f1 100644 +--- a/board/sunxi/board.c ++++ b/board/sunxi/board.c +@@ -666,6 +666,12 @@ void sunxi_board_init(void) + lradc_enable(); + #endif + ++#ifdef CONFIG_PINEPHONE_LEDS ++ /* PD18:G PD19:R PD20:B */ ++ gpio_request(SUNXI_GPD(19), "led:red"); ++ gpio_direction_output(SUNXI_GPD(19), 1); ++#endif ++ + #ifdef CONFIG_SY8106A_POWER + power_failed = sy8106a_set_vout1(CONFIG_SY8106A_VOUT1_VOLT); + #endif +diff --git a/configs/pinephone_defconfig b/configs/pinephone_defconfig +index 64ecef59c9..623265d719 100644 +--- a/configs/pinephone_defconfig ++++ b/configs/pinephone_defconfig +@@ -1,6 +1,7 @@ + CONFIG_ARM=y + CONFIG_ARCH_SUNXI=y + CONFIG_SPL=y ++CONFIG_PINEPHONE_LEDS=y + CONFIG_MACH_SUN50I=y + CONFIG_SUNXI_DRAM_LPDDR3_STOCK=y + CONFIG_DRAM_CLK=552 +-- +2.31.1 + diff --git a/dev-embedded/u-boot-pinephone-pro/files/1002-rockchip-Add-initial-support-for-the-PinePhone-Pro.patch b/dev-embedded/u-boot-pinephone-pro/files/1002-rockchip-Add-initial-support-for-the-PinePhone-Pro.patch deleted file mode 100644 index 3e48d2e..0000000 --- a/dev-embedded/u-boot-pinephone-pro/files/1002-rockchip-Add-initial-support-for-the-PinePhone-Pro.patch +++ /dev/null @@ -1,889 +0,0 @@ -From eea38c80ff858222e15ba4d79a0cb811adbdfc23 Mon Sep 17 00:00:00 2001 -From: Martijn Braam -Date: Sat, 12 Dec 2020 13:31:03 +0100 -Subject: [PATCH] rockchip: Add initial support for the PinePhone Pro - -This is a new device by PINE64 that's very similar to the Pinebook Pro -that's already supported. - -Specification: -- Rockchip RK3399 -- 4GB Dual-Channel LPDDR4 -- 128GB eMMC -- mSD card slot -- AP6255 for 802.11ac WiFi and Bluetooth -- 6 inch 720*1440 DSI display -- Quectel EG25g usb modem -- Type-C port with alt-mode display (DP 1.2) and PD charging. - -Signed-off-by: Martijn Braam ---- - arch/arm/dts/Makefile | 1 + - arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi | 44 ++ - arch/arm/dts/rk3399-pinephone-pro.dts | 520 ++++++++++++++++++ - arch/arm/mach-rockchip/rk3399/Kconfig | 8 + - board/pine64/pinephone-pro-rk3399/Kconfig | 15 + - board/pine64/pinephone-pro-rk3399/MAINTAINERS | 8 + - board/pine64/pinephone-pro-rk3399/Makefile | 1 + - .../pinephone-pro-rk3399.c | 57 ++ - configs/pinephone-pro-rk3399_defconfig | 92 ++++ - include/configs/pinephone-pro-rk3399.h | 23 + - 10 files changed, 769 insertions(+) - create mode 100644 arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi - create mode 100644 arch/arm/dts/rk3399-pinephone-pro.dts - create mode 100644 board/pine64/pinephone-pro-rk3399/Kconfig - create mode 100644 board/pine64/pinephone-pro-rk3399/MAINTAINERS - create mode 100644 board/pine64/pinephone-pro-rk3399/Makefile - create mode 100644 board/pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c - create mode 100644 configs/pinephone-pro-rk3399_defconfig - create mode 100644 include/configs/pinephone-pro-rk3399.h - -diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile -index aeaec713..6f123425 100644 ---- a/arch/arm/dts/Makefile -+++ b/arch/arm/dts/Makefile -@@ -145,6 +145,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \ - rk3399-nanopi-r4s.dtb \ - rk3399-orangepi.dtb \ - rk3399-pinebook-pro.dtb \ -+ rk3399-pinephone-pro.dtb \ - rk3399-puma-haikou.dtb \ - rk3399-roc-pc.dtb \ - rk3399-roc-pc-mezzanine.dtb \ -diff --git a/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi b/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi -new file mode 100644 -index 00000000..9d44db59 ---- /dev/null -+++ b/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi -@@ -0,0 +1,44 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright (C) 2019 Peter Robinson -+ * Copyright (C) 2021 Martijn Braam -+ */ -+ -+#include "rk3399-u-boot.dtsi" -+#include "rk3399-sdram-lpddr4-100.dtsi" -+ -+/ { -+ aliases { -+ spi0 = &spi1; -+ }; -+ -+ chosen { -+ u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc; -+ }; -+ -+ config { -+ u-boot,spl-payload-offset = <0x60000>; /* @ 384KB */ -+ }; -+}; -+ -+&i2c0 { -+ u-boot,dm-pre-reloc; -+}; -+ -+&rk818 { -+ u-boot,dm-pre-reloc; -+}; -+ -+&rng { -+ status = "okay"; -+}; -+ -+&sdhci { -+ max-frequency = <25000000>; -+ u-boot,dm-pre-reloc; -+}; -+ -+&sdmmc { -+ max-frequency = <20000000>; -+ u-boot,dm-pre-reloc; -+}; -diff --git a/arch/arm/dts/rk3399-pinephone-pro.dts b/arch/arm/dts/rk3399-pinephone-pro.dts -new file mode 100644 -index 00000000..3fe1845c ---- /dev/null -+++ b/arch/arm/dts/rk3399-pinephone-pro.dts -@@ -0,0 +1,520 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright (c) 2021 Martijn Braam -+ */ -+ -+/dts-v1/; -+#include "rk3399.dtsi" -+#include "rk3399-opp.dtsi" -+ -+/ { -+ model = "Pine64 PinePhone Pro"; -+ compatible = "pine64,pinephone-pro", "rockchip,rk3399"; -+ -+ chosen { -+ stdout-path = "serial2:1500000n8"; -+ }; -+ -+ sdio_pwrseq: sdio-pwrseq { -+ compatible = "mmc-pwrseq-simple"; -+ pinctrl-names = "default"; -+ }; -+ -+ /* Power tree */ -+ /* Root power source */ -+ vcc_sysin: vcc-sysin { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc_sysin"; -+ regulator-always-on; -+ regulator-boot-on; -+ }; -+ -+ /* Main 3.3v supply */ -+ vcc3v3_sys: vcc3v3-sys { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc3v3_sys"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ vin-supply = <&vcc_sysin>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ }; -+ }; -+}; -+ -+&cpu_l0 { -+ cpu-supply = <&vdd_cpu_l>; -+}; -+ -+&cpu_l1 { -+ cpu-supply = <&vdd_cpu_l>; -+}; -+ -+&cpu_l2 { -+ cpu-supply = <&vdd_cpu_l>; -+}; -+ -+&cpu_l3 { -+ cpu-supply = <&vdd_cpu_l>; -+}; -+ -+&cpu_b0 { -+ cpu-supply = <&vdd_cpu_b>; -+}; -+ -+&cpu_b1 { -+ cpu-supply = <&vdd_cpu_b>; -+}; -+ -+&emmc_phy { -+ status = "okay"; -+}; -+ -+&gpu { -+ mali-supply = <&vdd_gpu>; -+ status = "okay"; -+}; -+ -+&i2c0 { -+ clock-frequency = <400000>; -+ i2c-scl-rising-time-ns = <168>; -+ i2c-scl-falling-time-ns = <4>; -+ status = "okay"; -+ -+ rk818: pmic@1c { -+ compatible = "rockchip,rk818"; -+ reg = <0x1c>; -+ interrupt-parent = <&gpio1>; -+ interrupts = ; -+ #clock-cells = <1>; -+ clock-output-names = "xin32k", "rk808-clkout2"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pmic_int_l>; -+ rockchip,system-power-controller; -+ wakeup-source; -+ -+ vcc1-supply = <&vcc_sysin>; -+ vcc2-supply = <&vcc_sysin>; -+ vcc3-supply = <&vcc_sysin>; -+ vcc4-supply = <&vcc_sysin>; -+ vcc6-supply = <&vcc_sysin>; -+ vcc7-supply = <&vcc3v3_sys>; -+ vcc8-supply = <&vcc_sysin>; -+ vcc9-supply = <&vcc3v3_sys>; -+ -+ regulators { -+ vdd_cpu_l: DCDC_REG1 { -+ regulator-name = "vdd_cpu_1"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <750000>; -+ regulator-max-microvolt = <1350000>; -+ regulator-ramp-delay = <6001>; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdd_center: DCDC_REG2 { -+ regulator-name = "vdd_center"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <800000>; -+ regulator-max-microvolt = <1350000>; -+ regulator-ramp-delay = <6001>; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc_ddr: DCDC_REG3 { -+ regulator-name = "vcc_ddr"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ }; -+ }; -+ -+ vcc_1v8: DCDC_REG4 { -+ regulator-name = "vcc_1v8"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1800000>; -+ }; -+ }; -+ -+ vcca3v0_codec: LDO_REG1 { -+ regulator-name = "vcca3v0_codec"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3000000>; -+ regulator-max-microvolt = <3000000>; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc3v0_touch: LDO_REG2 { -+ regulator-name = "vcc3v0_touch"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3000000>; -+ regulator-max-microvolt = <3000000>; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcca1v8_codec: LDO_REG3 { -+ regulator-name = "vcca1v8_codec"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc_power_on: LDO_REG4 { -+ regulator-name = "vcc_power_on"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <3300000>; -+ }; -+ }; -+ -+ vcc_3v0: LDO_REG5 { -+ regulator-name = "vcc_3v0"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3000000>; -+ regulator-max-microvolt = <3000000>; -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <3000000>; -+ }; -+ }; -+ -+ vcc_1v5: LDO_REG6 { -+ regulator-name = "vcc_1v5"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1500000>; -+ regulator-max-microvolt = <1500000>; -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1500000>; -+ }; -+ }; -+ -+ vcc1v8_dvp: LDO_REG7 { -+ regulator-name = "vcc1v8_dvp"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc3v3_s3: LDO_REG8 { -+ regulator-name = "vcc3v3_s3"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc_sd: LDO_REG9 { -+ regulator-name = "vcc_sd"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <3300000>; -+ }; -+ }; -+ -+ vcc3v3_s0: SWITCH_REG { -+ regulator-name = "vcc3v3_s0"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ }; -+ }; -+ -+ boost_otg: DCDC_BOOST { -+ regulator-name = "boost_otg"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <5000000>; -+ }; -+ }; -+ -+ otg_switch: OTG_SWITCH { -+ regulator-name = "otg_switch"; -+ }; -+ }; -+ }; -+ -+ vdd_cpu_b: regulator@40 { -+ compatible = "silergy,syr827"; -+ reg = <0x40>; -+ fcs,suspend-voltage-selector = <1>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&vsel1_pin>; -+ regulator-name = "vdd_cpu_b"; -+ regulator-min-microvolt = <712500>; -+ regulator-max-microvolt = <1500000>; -+ regulator-ramp-delay = <1000>; -+ regulator-always-on; -+ regulator-boot-on; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdd_gpu: regulator@41 { -+ compatible = "silergy,syr828"; -+ reg = <0x41>; -+ fcs,suspend-voltage-selector = <1>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&vsel2_pin>; -+ regulator-name = "vdd_gpu"; -+ regulator-min-microvolt = <712500>; -+ regulator-max-microvolt = <1500000>; -+ regulator-ramp-delay = <1000>; -+ regulator-always-on; -+ regulator-boot-on; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+}; -+ -+&i2c1 { -+ i2c-scl-rising-time-ns = <300>; -+ i2c-scl-falling-time-ns = <15>; -+ status = "okay"; -+}; -+ -+&i2c3 { -+ i2c-scl-rising-time-ns = <450>; -+ i2c-scl-falling-time-ns = <15>; -+ status = "okay"; -+}; -+ -+&i2c4 { -+ i2c-scl-rising-time-ns = <600>; -+ i2c-scl-falling-time-ns = <20>; -+ status = "okay"; -+ -+ fusb0: typec-portc@22 { -+ compatible = "fcs,fusb302"; -+ reg = <0x22>; -+ interrupt-parent = <&gpio1>; -+ interrupts = ; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&fusb0_int>; -+ status = "okay"; -+ }; -+}; -+ -+&io_domains { -+ status = "okay"; -+ -+ bt656-supply = <&vcc1v8_dvp>; -+ audio-supply = <&vcca1v8_codec>; -+ sdmmc-supply = <&vcc_sd>; -+ gpio1830-supply = <&vcc_3v0>; -+}; -+ -+&pmu_io_domains { -+ pmu1830-supply = <&vcc_3v0>; -+ status = "okay"; -+}; -+ -+&pinctrl { -+ bt { -+ bt_enable_h: bt-enable-h { -+ rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ bt_host_wake_l: bt-host-wake-l { -+ rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_down>; -+ }; -+ -+ bt_wake_l: bt-wake-l { -+ rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ buttons { -+ pwrbtn: pwrbtn { -+ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ }; -+ -+ fusb302x { -+ fusb0_int: fusb0-int { -+ rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ }; -+ -+ leds { -+ work_led_pin: work-led-pin { -+ rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ diy_led_pin: diy-led-pin { -+ rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ pcie { -+ pcie_perst: pcie-perst { -+ rockchip,pins = <2 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ pcie_pwr_en: pcie-pwr-en { -+ rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ pmic { -+ pmic_int_l: pmic-int-l { -+ rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ -+ vsel1_pin: vsel1-pin { -+ rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; -+ }; -+ -+ vsel2_pin: vsel2-pin { -+ rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; -+ }; -+ }; -+ -+ sdcard { -+ sdmmc0_pwr_h: sdmmc0-pwr-h { -+ rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ }; -+ -+ sdio-pwrseq { -+ wifi_enable_h: wifi-enable-h { -+ rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ usb-typec { -+ vcc5v0_typec_en: vcc5v0_typec_en { -+ rockchip,pins = <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ }; -+ -+ usb2 { -+ vcc5v0_host_en: vcc5v0-host-en { -+ rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+}; -+ -+&pwm0 { -+ status = "okay"; -+}; -+ -+&pwm1 { -+ status = "okay"; -+}; -+ -+&pwm2 { -+ status = "okay"; -+}; -+ -+&sdio0 { -+ bus-width = <4>; -+ cap-sd-highspeed; -+ cap-sdio-irq; -+ disable-wp; -+ keep-power-in-suspend; -+ mmc-pwrseq = <&sdio_pwrseq>; -+ non-removable; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; -+ sd-uhs-sdr104; -+ status = "okay"; -+}; -+ -+&sdmmc { -+ bus-width = <4>; -+ cap-sd-highspeed; -+ cd-gpios = <&gpio0 7 GPIO_ACTIVE_LOW>; -+ disable-wp; -+ max-frequency = <150000000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>; -+ vmmc-supply = <&vcc3v3_s3>; -+ vqmmc-supply = <&vcc_1v8>; -+ status = "okay"; -+}; -+ -+&sdhci { -+ bus-width = <8>; -+ mmc-hs200-1_8v; -+ non-removable; -+ status = "okay"; -+}; -+ -+&tsadc { -+ /* tshut mode 0:CRU 1:GPIO */ -+ rockchip,hw-tshut-mode = <1>; -+ /* tshut polarity 0:LOW 1:HIGH */ -+ rockchip,hw-tshut-polarity = <1>; -+ status = "okay"; -+}; -+ -+&uart2 { -+ status = "okay"; -+}; -+ -+&vopb { -+ status = "okay"; -+}; -+ -+&vopb_mmu { -+ status = "okay"; -+}; -+ -+&vopl { -+ status = "okay"; -+}; -+ -+&vopl_mmu { -+ status = "okay"; -+}; -diff --git a/arch/arm/mach-rockchip/rk3399/Kconfig b/arch/arm/mach-rockchip/rk3399/Kconfig -index 17628f91..3ba603ca 100644 ---- a/arch/arm/mach-rockchip/rk3399/Kconfig -+++ b/arch/arm/mach-rockchip/rk3399/Kconfig -@@ -28,6 +28,13 @@ config TARGET_PINEBOOK_PRO_RK3399 - with 4Gb RAM, onboard eMMC, USB-C, a USB3 and USB2 port, - 1920*1080 screen and all the usual laptop features. - -+config TARGET_PINEPHONE_PRO_RK3399 -+ bool "PinePhone Pro" -+ help -+ PinePhone Pro is a phone based on the Rockchip rk3399 SoC -+ with 4Gb RAM, onboard eMMC, USB-C, a headphone jack, -+ 720x1440 screen and an external Quectel USB modem. -+ - config TARGET_PUMA_RK3399 - bool "Theobroma Systems RK3399-Q7 (Puma)" - help -@@ -154,6 +161,7 @@ endif # BOOTCOUNT_LIMIT - source "board/firefly/roc-pc-rk3399/Kconfig" - source "board/google/gru/Kconfig" - source "board/pine64/pinebook-pro-rk3399/Kconfig" -+source "board/pine64/pinephone-pro-rk3399/Kconfig" - source "board/pine64/rockpro64_rk3399/Kconfig" - source "board/rockchip/evb_rk3399/Kconfig" - source "board/theobroma-systems/puma_rk3399/Kconfig" -diff --git a/board/pine64/pinephone-pro-rk3399/Kconfig b/board/pine64/pinephone-pro-rk3399/Kconfig -new file mode 100644 -index 00000000..13d6465a ---- /dev/null -+++ b/board/pine64/pinephone-pro-rk3399/Kconfig -@@ -0,0 +1,15 @@ -+if TARGET_PINEPHONE_PRO_RK3399 -+ -+config SYS_BOARD -+ default "pinephone-pro-rk3399" -+ -+config SYS_VENDOR -+ default "pine64" -+ -+config SYS_CONFIG_NAME -+ default "pinephone-pro-rk3399" -+ -+config BOARD_SPECIFIC_OPTIONS -+ def_bool y -+ -+endif -diff --git a/board/pine64/pinephone-pro-rk3399/MAINTAINERS b/board/pine64/pinephone-pro-rk3399/MAINTAINERS -new file mode 100644 -index 00000000..9ca4fc4c ---- /dev/null -+++ b/board/pine64/pinephone-pro-rk3399/MAINTAINERS -@@ -0,0 +1,8 @@ -+PINEPHONE_PRO -+M: Martijn Braam -+S: Maintained -+F: board/pine64/rk3399-pinephone-pro/ -+F: include/configs/rk3399-pinephone-pro.h -+F: arch/arm/dts/rk3399-pinephone-pro.dts -+F: arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi -+F: configs/pinephone-pro-rk3399_defconfig -diff --git a/board/pine64/pinephone-pro-rk3399/Makefile b/board/pine64/pinephone-pro-rk3399/Makefile -new file mode 100644 -index 00000000..8d920305 ---- /dev/null -+++ b/board/pine64/pinephone-pro-rk3399/Makefile -@@ -0,0 +1 @@ -+obj-y += pinephone-pro-rk3399.o -diff --git a/board/pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c b/board/pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c -new file mode 100644 -index 00000000..8efeb6ea ---- /dev/null -+++ b/board/pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c -@@ -0,0 +1,57 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * (C) Copyright 2019 Vasily Khoruzhick -+ * (C) Copyright 2021 Martijn Braam -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define GRF_IO_VSEL_BT565_SHIFT 0 -+#define PMUGRF_CON0_VSEL_SHIFT 8 -+ -+#ifdef CONFIG_MISC_INIT_R -+static void setup_iodomain(void) -+{ -+ struct rk3399_grf_regs *grf = -+ syscon_get_first_range(ROCKCHIP_SYSCON_GRF); -+ struct rk3399_pmugrf_regs *pmugrf = -+ syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF); -+ -+ /* BT565 is in 1.8v domain */ -+ rk_setreg(&grf->io_vsel, 1 << GRF_IO_VSEL_BT565_SHIFT); -+ -+ /* Set GPIO1 1.8v/3.0v source select to PMU1830_VOL */ -+ rk_setreg(&pmugrf->soc_con0, 1 << PMUGRF_CON0_VSEL_SHIFT); -+} -+ -+int misc_init_r(void) -+{ -+ const u32 cpuid_offset = 0x7; -+ const u32 cpuid_length = 0x10; -+ u8 cpuid[cpuid_length]; -+ int ret; -+ -+ setup_iodomain(); -+ -+ ret = rockchip_cpuid_from_efuse(cpuid_offset, cpuid_length, cpuid); -+ if (ret) -+ return ret; -+ -+ ret = rockchip_cpuid_set(cpuid, cpuid_length); -+ if (ret) -+ return ret; -+ -+ ret = rockchip_setup_macaddr(); -+ -+ return ret; -+} -+ -+#endif -diff --git a/configs/pinephone-pro-rk3399_defconfig b/configs/pinephone-pro-rk3399_defconfig -new file mode 100644 -index 00000000..2cf80f7d ---- /dev/null -+++ b/configs/pinephone-pro-rk3399_defconfig -@@ -0,0 +1,92 @@ -+CONFIG_ARM=y -+CONFIG_SKIP_LOWLEVEL_INIT=y -+CONFIG_ARCH_ROCKCHIP=y -+CONFIG_SYS_TEXT_BASE=0x00200000 -+CONFIG_NR_DRAM_BANKS=1 -+CONFIG_ENV_SIZE=0x8000 -+CONFIG_ROCKCHIP_RK3399=y -+CONFIG_TARGET_PINEPHONE_PRO_RK3399=y -+CONFIG_DEBUG_UART_BASE=0xFF1A0000 -+CONFIG_DEBUG_UART_CLOCK=24000000 -+CONFIG_SPL_SPI_FLASH_SUPPORT=y -+CONFIG_SPL_SPI_SUPPORT=y -+CONFIG_DEFAULT_DEVICE_TREE="rk3399-pinephone-pro" -+CONFIG_DEBUG_UART=y -+CONFIG_SYS_LOAD_ADDR=0x800800 -+CONFIG_BOOTDELAY=3 -+CONFIG_USE_PREBOOT=y -+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-pinephone-pro.dtb" -+CONFIG_DISPLAY_BOARDINFO_LATE=y -+CONFIG_MISC_INIT_R=y -+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -+CONFIG_SPL_STACK_R=y -+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 -+CONFIG_SPL_MTD_SUPPORT=y -+CONFIG_SPL_SPI_LOAD=y -+CONFIG_TPL=y -+CONFIG_CMD_BOOTZ=y -+CONFIG_CMD_GPIO=y -+CONFIG_CMD_GPT=y -+CONFIG_CMD_I2C=y -+CONFIG_CMD_MMC=y -+CONFIG_CMD_PCI=y -+CONFIG_CMD_USB=y -+# CONFIG_CMD_SETEXPR is not set -+CONFIG_CMD_TIME=y -+CONFIG_CMD_PMIC=y -+CONFIG_CMD_REGULATOR=y -+CONFIG_SPL_OF_CONTROL=y -+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" -+CONFIG_ENV_IS_IN_SPI_FLASH=y -+CONFIG_SYS_RELOC_GD_ENV_ADDR=y -+CONFIG_ROCKCHIP_GPIO=y -+CONFIG_SYS_I2C_ROCKCHIP=y -+CONFIG_DM_KEYBOARD=y -+CONFIG_LED=y -+CONFIG_LED_GPIO=y -+CONFIG_MISC=y -+CONFIG_ROCKCHIP_EFUSE=y -+CONFIG_MMC_DW=y -+CONFIG_MMC_DW_ROCKCHIP=y -+CONFIG_MMC_SDHCI=y -+CONFIG_MMC_SDHCI_SDMA=y -+CONFIG_MMC_SDHCI_ROCKCHIP=y -+CONFIG_SF_DEFAULT_SPEED=20000000 -+CONFIG_SPI_FLASH_GIGADEVICE=y -+CONFIG_SPI_FLASH_WINBOND=y -+CONFIG_DM_ETH=y -+CONFIG_PHY_ROCKCHIP_INNO_USB2=y -+CONFIG_PHY_ROCKCHIP_TYPEC=y -+CONFIG_DM_PMIC_FAN53555=y -+CONFIG_PMIC_RK8XX=y -+CONFIG_REGULATOR_PWM=y -+CONFIG_REGULATOR_RK8XX=y -+CONFIG_PWM_ROCKCHIP=y -+CONFIG_RAM_RK3399_LPDDR4=y -+CONFIG_DM_RESET=y -+CONFIG_DM_RNG=y -+CONFIG_RNG_ROCKCHIP=y -+CONFIG_BAUDRATE=1500000 -+CONFIG_DEBUG_UART_SHIFT=2 -+CONFIG_ROCKCHIP_SPI=y -+CONFIG_SYSRESET=y -+CONFIG_USB=y -+CONFIG_USB_XHCI_HCD=y -+CONFIG_USB_XHCI_DWC3=y -+CONFIG_USB_EHCI_HCD=y -+CONFIG_USB_EHCI_GENERIC=y -+CONFIG_USB_OHCI_HCD=y -+CONFIG_USB_OHCI_GENERIC=y -+CONFIG_USB_DWC3=y -+CONFIG_USB_DWC3_GENERIC=y -+CONFIG_USB_KEYBOARD=y -+CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y -+CONFIG_USB_HOST_ETHER=y -+CONFIG_USB_ETHER_ASIX=y -+CONFIG_USB_ETHER_RTL8152=y -+CONFIG_DM_VIDEO=y -+CONFIG_DISPLAY=y -+CONFIG_VIDEO_ROCKCHIP=y -+CONFIG_DISPLAY_ROCKCHIP_EDP=y -+CONFIG_SPL_TINY_MEMSET=y -+CONFIG_ERRNO_STR=y -diff --git a/include/configs/pinephone-pro-rk3399.h b/include/configs/pinephone-pro-rk3399.h -new file mode 100644 -index 00000000..fefa793f ---- /dev/null -+++ b/include/configs/pinephone-pro-rk3399.h -@@ -0,0 +1,23 @@ -+/* SPDX-License-Identifier: GPL-2.0+ */ -+/* -+ * Copyright (C) 2016 Rockchip Electronics Co., Ltd -+ * Copyright (C) 2020 Peter Robinson -+ * Copyright (C) 2021 Martijn Braam -+ */ -+ -+#ifndef __PINEPHONE_PRO_RK3399_H -+#define __PINEPHONE_PRO_RK3399_H -+ -+#define ROCKCHIP_DEVICE_SETTINGS \ -+ "stdin=serial,usbkbd\0" \ -+ "stdout=serial,vidconsole\0" \ -+ "stderr=serial,vidconsole\0" -+ -+#include -+ -+#define SDRAM_BANK_SIZE (2UL << 30) -+ -+#define CONFIG_USB_OHCI_NEW -+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 -+ -+#endif --- -2.34.1 - diff --git a/dev-embedded/u-boot-pinephone-pro/files/1003-mmc-sunxi-Add-support-for-DMA-transfers.patch b/dev-embedded/u-boot-pinephone-pro/files/1003-mmc-sunxi-Add-support-for-DMA-transfers.patch new file mode 100644 index 0000000..9be832c --- /dev/null +++ b/dev-embedded/u-boot-pinephone-pro/files/1003-mmc-sunxi-Add-support-for-DMA-transfers.patch @@ -0,0 +1,354 @@ +From b0950e4696b391578f7428337e41fa8ca14b225d Mon Sep 17 00:00:00 2001 +From: Ondrej Jirman +Date: Wed, 11 Sep 2019 20:45:28 +0200 +Subject: [PATCH 27/29] mmc: sunxi: Add support for DMA transfers + +Allwinner MMC controller supports DMA via internal DMA controller, +use it. + +Signed-off-by: Ondrej Jirman +--- + arch/arm/include/asm/arch-sunxi/mmc.h | 7 + + drivers/mmc/sunxi_mmc.c | 204 +++++++++++++++++++++++--- + 2 files changed, 192 insertions(+), 19 deletions(-) + +diff --git a/arch/arm/include/asm/arch-sunxi/mmc.h b/arch/arm/include/asm/arch-sunxi/mmc.h +index 5daacf10eb..dc8ea6f43a 100644 +--- a/arch/arm/include/asm/arch-sunxi/mmc.h ++++ b/arch/arm/include/asm/arch-sunxi/mmc.h +@@ -112,6 +112,10 @@ struct sunxi_mmc { + SUNXI_MMC_RINT_COMMAND_DONE | \ + SUNXI_MMC_RINT_VOLTAGE_CHANGE_DONE) + ++#define SUNXI_MMC_FTRGLEVEL_BURST_SIZE(v) (((v) & 0x7) << 28) ++#define SUNXI_MMC_FTRGLEVEL_RX_TL(v) (((v) & 0xfff) << 16) ++#define SUNXI_MMC_FTRGLEVEL_TX_TL(v) (((v) & 0xffff) << 0) ++ + #define SUNXI_MMC_STATUS_RXWL_FLAG (0x1 << 0) + #define SUNXI_MMC_STATUS_TXWL_FLAG (0x1 << 1) + #define SUNXI_MMC_STATUS_FIFO_EMPTY (0x1 << 2) +@@ -130,6 +134,9 @@ struct sunxi_mmc { + #define SUNXI_MMC_IDIE_TXIRQ (0x1 << 0) + #define SUNXI_MMC_IDIE_RXIRQ (0x1 << 1) + ++#define SUNXI_MMC_IDST_TXIRQ (0x1 << 0) ++#define SUNXI_MMC_IDST_RXIRQ (0x1 << 1) ++ + #define SUNXI_MMC_COMMON_CLK_GATE (1 << 16) + #define SUNXI_MMC_COMMON_RESET (1 << 18) + +diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c +index 28af8e6ac5..47c947cdb8 100644 +--- a/drivers/mmc/sunxi_mmc.c ++++ b/drivers/mmc/sunxi_mmc.c +@@ -9,6 +9,7 @@ + + #include + #include ++#include + #include + #include + #include +@@ -27,6 +28,27 @@ + #define CCM_MMC_CTRL_MODE_SEL_NEW 0 + #endif + ++#define DMA_CONFIG_DIC BIT(1) // flag: disable interrupt after this descriptor's buffer is processed ++#define DMA_CONFIG_LAST BIT(2) // flag: last descriptor ++#define DMA_CONFIG_FIRST BIT(3) // flag: first descriptor ++#define DMA_CONFIG_CHAIN BIT(4) // flag: buf_addr_ptr2 points to next descriptor ++#define DMA_CONFIG_ERROR BIT(30) // flag: out: error happened ++#define DMA_CONFIG_HOLD BIT(31) // flag: desc owned by IDMAC (set to 1) ++ ++#if defined(CONFIG_MACH_SUN50I) ++// mmc2 on A64 only allows for 8k ++#define DMA_BUF_MAX_SIZE (1 << 13) ++#else ++#define DMA_BUF_MAX_SIZE (1 << 16) ++#endif ++ ++struct sunxi_idma_desc { ++ u32 config; ++ u32 buf_size; ++ u32 buf_addr_ptr1; ++ u32 buf_addr_ptr2; ++}; ++ + struct sunxi_mmc_plat { + struct mmc_config cfg; + struct mmc mmc; +@@ -39,6 +61,8 @@ struct sunxi_mmc_priv { + struct gpio_desc cd_gpio; /* Change Detect GPIO */ + struct sunxi_mmc *reg; + struct mmc_config cfg; ++ unsigned n_dma_descs; ++ struct sunxi_idma_desc* dma_descs; + }; + + #if !CONFIG_IS_ENABLED(DM_MMC) +@@ -318,7 +342,7 @@ static int mmc_trans_data_by_cpu(struct sunxi_mmc_priv *priv, struct mmc *mmc, + if (timeout_msecs < 2000) + timeout_msecs = 2000; + +- /* Always read / write data through the CPU */ ++ /* Read / write data through the CPU */ + setbits_le32(&priv->reg->gctrl, SUNXI_MMC_GCTRL_ACCESS_BY_AHB); + + start = get_timer(0); +@@ -328,7 +352,7 @@ static int mmc_trans_data_by_cpu(struct sunxi_mmc_priv *priv, struct mmc *mmc, + + while ((status = readl(&priv->reg->status)) & status_bit) { + if (get_timer(start) > timeout_msecs) +- return -1; ++ return -ETIMEDOUT; + } + + /* +@@ -360,21 +384,142 @@ static int mmc_trans_data_by_cpu(struct sunxi_mmc_priv *priv, struct mmc *mmc, + return 0; + } + ++static void flush_cache_auto_align(void* buf, size_t len) ++{ ++ uintptr_t mask = ~((uintptr_t)CONFIG_SYS_CACHELINE_SIZE - 1); ++ uintptr_t start = (uintptr_t)buf & mask; ++ ++ len = (len + 2 * CONFIG_SYS_CACHELINE_SIZE) & mask; ++ ++ flush_cache(start, len); ++} ++ ++static int mmc_trans_data_by_dma(struct sunxi_mmc_priv *priv, struct mmc *mmc, ++ struct mmc_data *data) ++{ ++ const int reading = !!(data->flags & MMC_DATA_READ); ++ uint8_t *buff = (uint8_t*)(reading ? data->dest : data->src); ++ unsigned byte_cnt = data->blocksize * data->blocks; ++ unsigned i, n_desc, last_block_size; ++ u32 rval; ++ ++ /* data pointer and transfer size needs to be aligned to 4 bytes */ ++ ++ /* Read / write data through IDMAC */ ++ clrbits_le32(&priv->reg->gctrl, SUNXI_MMC_GCTRL_ACCESS_BY_AHB); ++ ++ n_desc = byte_cnt / DMA_BUF_MAX_SIZE; ++ last_block_size = byte_cnt % DMA_BUF_MAX_SIZE; ++ if (last_block_size) ++ n_desc++; ++ ++ if (n_desc > priv->n_dma_descs) ++ return -ENOMEM; ++ ++ memset(priv->dma_descs, 0, sizeof(struct sunxi_idma_desc) * n_desc); ++ ++ for (i = 0; i < n_desc; i++) { ++ struct sunxi_idma_desc* desc = &priv->dma_descs[i]; ++ bool is_last = i == n_desc - 1; ++ bool is_first = i == 0; ++ ++ desc->config = DMA_CONFIG_CHAIN | DMA_CONFIG_HOLD ++ | (is_last ? DMA_CONFIG_LAST : DMA_CONFIG_DIC) ++ | (is_first ? DMA_CONFIG_FIRST : 0); ++ ++ if (is_last && last_block_size) ++ desc->buf_size = last_block_size; ++ else ++ desc->buf_size = DMA_BUF_MAX_SIZE; ++ ++ desc->buf_addr_ptr1 = (uintptr_t)buff + i * DMA_BUF_MAX_SIZE; ++ if (!is_last) ++ desc->buf_addr_ptr2 = (uintptr_t)(desc + 1); ++ } ++ ++ /* ++ * Make sure everyhting needed for a transfer is in DRAM. ++ */ ++ ++ flush_cache_auto_align(buff, byte_cnt); ++ flush_cache_auto_align(priv->dma_descs, ++ sizeof(struct sunxi_idma_desc) * n_desc); ++ ++ dsb(); ++ isb(); ++ ++ /* dma enable */ ++ setbits_le32(&priv->reg->gctrl, SUNXI_MMC_GCTRL_DMA_RESET ++ | SUNXI_MMC_GCTRL_DMA_ENABLE); ++ ++ /* idma reset */ ++ writel(SUNXI_MMC_IDMAC_RESET, &priv->reg->dmac); ++ ++ /* wait idma reset done */ ++ while (readl(&priv->reg->dmac) & SUNXI_MMC_IDMAC_RESET); ++ ++ /* idma on */ ++ writel(SUNXI_MMC_IDMAC_ENABLE | SUNXI_MMC_IDMAC_FIXBURST, ++ &priv->reg->dmac); ++ ++ /* enable interrupt flags */ ++ rval = readl(&priv->reg->idie) ++ & ~(SUNXI_MMC_IDIE_RXIRQ | SUNXI_MMC_IDIE_TXIRQ); ++ rval |= reading ? SUNXI_MMC_IDIE_RXIRQ : SUNXI_MMC_IDIE_TXIRQ; ++ writel(rval, &priv->reg->idie); ++ ++ /* set address of the first descriptor */ ++ writel((uintptr_t)priv->dma_descs, &priv->reg->dlba); ++ ++ /* set fifo fill tresholds for issuing dma */ ++ ++#if defined(CONFIG_MACH_SUN50I) || defined(CONFIG_MACH_SUN50I_H6) ++ if (priv->mmc_no == 2) { ++ // for mmc 2 we need to set this differently ++ writel(SUNXI_MMC_FTRGLEVEL_BURST_SIZE(3) // burst-16 ++ | SUNXI_MMC_FTRGLEVEL_RX_TL(15) ++ | SUNXI_MMC_FTRGLEVEL_TX_TL(240), ++ &priv->reg->ftrglevel); ++ } else { ++ writel(SUNXI_MMC_FTRGLEVEL_BURST_SIZE(2) // burst-8 ++ | SUNXI_MMC_FTRGLEVEL_RX_TL(7) ++ | SUNXI_MMC_FTRGLEVEL_TX_TL(248), ++ &priv->reg->ftrglevel); ++ } ++#else ++ writel(SUNXI_MMC_FTRGLEVEL_BURST_SIZE(2) // burst-8 ++ | SUNXI_MMC_FTRGLEVEL_RX_TL(7) ++ | SUNXI_MMC_FTRGLEVEL_TX_TL(8), ++ &priv->reg->ftrglevel); ++#endif ++ ++ writel(0xffffffff, &priv->reg->idst); ++ ++ return 0; ++} ++ + static int mmc_rint_wait(struct sunxi_mmc_priv *priv, struct mmc *mmc, +- uint timeout_msecs, uint done_bit, const char *what) ++ uint timeout_msecs, uint done_bit, bool wait_dma, ++ const char *what) + { + unsigned int status; + unsigned long start = get_timer(0); ++ bool dma_done = true; + + do { + status = readl(&priv->reg->rint); ++ + if ((get_timer(start) > timeout_msecs) || + (status & SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT)) { + debug("%s timeout %x\n", what, + status & SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT); + return -ETIMEDOUT; + } +- } while (!(status & done_bit)); ++ ++ if (wait_dma) ++ dma_done = readl(&priv->reg->idst) ++ & (SUNXI_MMC_IDST_TXIRQ | SUNXI_MMC_IDST_RXIRQ); ++ } while (!(status & done_bit) || !dma_done); + + return 0; + } +@@ -388,6 +533,7 @@ static int sunxi_mmc_send_cmd_common(struct sunxi_mmc_priv *priv, + int error = 0; + unsigned int status = 0; + unsigned int bytecnt = 0; ++ bool usedma = false; + + if (priv->fatal_err) + return -1; +@@ -424,42 +570,45 @@ static int sunxi_mmc_send_cmd_common(struct sunxi_mmc_priv *priv, + cmd->cmdidx, cmdval | cmd->cmdidx, cmd->cmdarg); + writel(cmd->cmdarg, &priv->reg->arg); + +- if (!data) +- writel(cmdval | cmd->cmdidx, &priv->reg->cmd); +- + /* + * transfer data and check status + * STATREG[2] : FIFO empty + * STATREG[3] : FIFO full + */ + if (data) { +- int ret = 0; +- + bytecnt = data->blocksize * data->blocks; + debug("trans data %d bytes\n", bytecnt); +- writel(cmdval | cmd->cmdidx, &priv->reg->cmd); +- ret = mmc_trans_data_by_cpu(priv, mmc, data); +- if (ret) { +- error = readl(&priv->reg->rint) & +- SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT; +- error = -ETIMEDOUT; +- goto out; ++ ++ if (bytecnt > 64 && !IS_ENABLED(SPL_BUILD)) { ++ debug(" using dma %d\n", bytecnt); ++ error = mmc_trans_data_by_dma(priv, mmc, data); ++ writel(cmdval | cmd->cmdidx, &priv->reg->cmd); ++ usedma = true; ++ } else { ++ debug(" using pio\n"); ++ writel(cmdval | cmd->cmdidx, &priv->reg->cmd); ++ error = mmc_trans_data_by_cpu(priv, mmc, data); + } ++ ++ if (error) ++ goto out; ++ } else { ++ writel(cmdval | cmd->cmdidx, &priv->reg->cmd); + } + + error = mmc_rint_wait(priv, mmc, 1000, SUNXI_MMC_RINT_COMMAND_DONE, +- "cmd"); ++ false, "cmd"); + if (error) + goto out; + + if (data) { +- timeout_msecs = 120; ++ timeout_msecs = 10000; + debug("cacl timeout %x msec\n", timeout_msecs); + error = mmc_rint_wait(priv, mmc, timeout_msecs, + data->blocks > 1 ? + SUNXI_MMC_RINT_AUTO_COMMAND_DONE : + SUNXI_MMC_RINT_DATA_OVER, +- "data"); ++ usedma, "data"); + if (error) + goto out; + } +@@ -491,6 +640,14 @@ static int sunxi_mmc_send_cmd_common(struct sunxi_mmc_priv *priv, + debug("mmc resp 0x%08x\n", cmd->response[0]); + } + out: ++ if (data && usedma) { ++ //status = readl(®->idst); ++ writel(0, &priv->reg->idie); ++ writel(0xffffffff, &priv->reg->idst); ++ writel(0, &priv->reg->dmac); ++ clrbits_le32(&priv->reg->gctrl, SUNXI_MMC_GCTRL_DMA_ENABLE); ++ } ++ + if (error < 0) { + writel(SUNXI_MMC_GCTRL_RESET, &priv->reg->gctrl); + mmc_update_clk(priv); +@@ -674,6 +831,15 @@ static int sunxi_mmc_probe(struct udevice *dev) + + priv->reg = dev_read_addr_ptr(dev); + ++ // make sure we have enough space for descritors for BLK_SIZE * b_max ++ priv->n_dma_descs = 512 * 65536 / DMA_BUF_MAX_SIZE; ++ priv->dma_descs = malloc(sizeof(struct sunxi_idma_desc) ++ * priv->n_dma_descs); ++ if (priv->dma_descs == NULL) { ++ debug("init mmc alloc failed\n"); ++ return -ENOMEM; ++ } ++ + /* We don't have a sunxi clock driver so find the clock address here */ + ret = dev_read_phandle_with_args(dev, "clocks", "#clock-cells", 0, + 1, &args); +-- +2.31.1 + diff --git a/dev-embedded/u-boot-pinephone-pro/files/1004-mmc-sunxi-DDR-DMA-support-for-SPL.patch b/dev-embedded/u-boot-pinephone-pro/files/1004-mmc-sunxi-DDR-DMA-support-for-SPL.patch new file mode 100644 index 0000000..ed5dae5 --- /dev/null +++ b/dev-embedded/u-boot-pinephone-pro/files/1004-mmc-sunxi-DDR-DMA-support-for-SPL.patch @@ -0,0 +1,50 @@ +From 1af4c86329397bc553122c650226bd5c7acb1ed0 Mon Sep 17 00:00:00 2001 +From: Ondrej Jirman +Date: Fri, 13 Sep 2019 22:14:43 +0200 +Subject: [PATCH 28/29] mmc: sunxi: DDR/DMA support for SPL + +--- + drivers/mmc/sunxi_mmc.c | 16 +++++++++++++++- + 1 file changed, 15 insertions(+), 1 deletion(-) + +diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c +index 47c947cdb8..855dfd35d9 100644 +--- a/drivers/mmc/sunxi_mmc.c ++++ b/drivers/mmc/sunxi_mmc.c +@@ -579,7 +579,12 @@ static int sunxi_mmc_send_cmd_common(struct sunxi_mmc_priv *priv, + bytecnt = data->blocksize * data->blocks; + debug("trans data %d bytes\n", bytecnt); + +- if (bytecnt > 64 && !IS_ENABLED(SPL_BUILD)) { ++ // DMA doesn't work when the target is SRAM for some reason. ++ int reading = !!(data->flags & MMC_DATA_READ); ++ uint8_t* buf = (uint8_t*)(reading ? data->dest : data->src); ++ bool is_dram = (uintptr_t)buf >= 0x4000000; ++ ++ if (bytecnt > 64 && is_dram) { + debug(" using dma %d\n", bytecnt); + error = mmc_trans_data_by_dma(priv, mmc, data); + writel(cmdval | cmd->cmdidx, &priv->reg->cmd); +@@ -715,10 +720,19 @@ struct mmc *sunxi_mmc_init(int sdc_no) + + cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS; + cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; ++ if (sdc_no == 2) ++ cfg->host_caps |= MMC_MODE_DDR_52MHz; + + cfg->f_min = 400000; + cfg->f_max = 52000000; + ++ // enough descs for a realy big u-boot (4MiB) ++ priv->n_dma_descs = 4*1024*1024 / DMA_BUF_MAX_SIZE; ++ priv->dma_descs = malloc(sizeof(struct sunxi_idma_desc) ++ * priv->n_dma_descs); ++ if (priv->dma_descs == NULL) ++ return NULL; ++ + if (mmc_resource_init(sdc_no) != 0) + return NULL; + +-- +2.31.1 + diff --git a/dev-embedded/u-boot-pinephone-pro/files/1004-mtd-spi-nor-ids-Add-GigaDevice-GD25LQ128E-entry.patch b/dev-embedded/u-boot-pinephone-pro/files/1004-mtd-spi-nor-ids-Add-GigaDevice-GD25LQ128E-entry.patch deleted file mode 100644 index 19a7892..0000000 --- a/dev-embedded/u-boot-pinephone-pro/files/1004-mtd-spi-nor-ids-Add-GigaDevice-GD25LQ128E-entry.patch +++ /dev/null @@ -1,28 +0,0 @@ -From 679d7562f4711b1ad8c5ea54aa804fde5da5a19d Mon Sep 17 00:00:00 2001 -From: Samuel Dionne-Riel -Date: Sat, 5 Feb 2022 21:00:53 -0500 -Subject: [PATCH] mtd: spi-nor-ids: Add GigaDevice GD25LQ128E entry - ---- - drivers/mtd/spi/spi-nor-ids.c | 5 +++++ - 1 file changed, 5 insertions(+) - -diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c -index 4aef1ddd6e2..ff5bc2b2d78 100644 ---- a/drivers/mtd/spi/spi-nor-ids.c -+++ b/drivers/mtd/spi/spi-nor-ids.c -@@ -112,6 +112,11 @@ const struct flash_info spi_nor_ids[] = { - SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | - SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) - }, -+ { -+ INFO("gd25lq128e", 0x257018, 0, 64 * 1024, 256, -+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | -+ SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) -+ }, - { - INFO("gd25q128", 0xc84018, 0, 64 * 1024, 256, - SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | --- -2.34.0 - diff --git a/dev-embedded/u-boot-pinephone-pro/files/1005-Reconfigure-GPIO4_D3-as-input-on-PinePhone-Pro.patch b/dev-embedded/u-boot-pinephone-pro/files/1005-Reconfigure-GPIO4_D3-as-input-on-PinePhone-Pro.patch deleted file mode 100644 index 8bf3b2a..0000000 --- a/dev-embedded/u-boot-pinephone-pro/files/1005-Reconfigure-GPIO4_D3-as-input-on-PinePhone-Pro.patch +++ /dev/null @@ -1,67 +0,0 @@ -From 7d114ec31e537fcb4c2e4f0fca867b050fd59549 Mon Sep 17 00:00:00 2001 -From: Dragan Simic -Date: Thu, 10 Feb 2022 14:43:05 +0100 -Subject: [PATCH] Reconfigure GPIO4_D3 as input on PinePhone Pro - ---- - .../pinephone-pro-rk3399.c | 39 ++++++++++++++++++- - 1 file changed, 38 insertions(+), 1 deletion(-) - -diff --git a/board/pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c b/board/pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c -index d79084614f..bc19b275b2 100644 ---- a/board/pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c -+++ b/board/pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c -@@ -12,6 +12,7 @@ - #include - #include - #include -+#include - - #define GRF_IO_VSEL_BT565_SHIFT 0 - #define PMUGRF_CON0_VSEL_SHIFT 8 -@@ -52,5 +53,41 @@ int misc_init_r(void) - - return ret; - } -- - #endif -+ -+#define GPIO4_D3 "155" -+ -+static int setup_gpios(void) -+{ -+ struct gpio_desc gpio; -+ int ret; -+ -+ /* -+ * MaskROM enables output on GPIO4_D3 and leaves it that way, seemingly -+ * because the RK3399 reference BOX and VR REF designs use GPIO4_D3 as -+ * EFUSE_VQPS (AD23) power control output, while it is a light sensor -+ * interrupt on the PinePhone Pro and needs to be configured as input. -+ */ -+ ret = dm_gpio_lookup_name(GPIO4_D3, &gpio); -+ if (ret) -+ return ret; -+ -+ ret = dm_gpio_request(&gpio, "light_int_l"); -+ if (ret) -+ return ret; -+ -+ dm_gpio_set_dir_flags(&gpio, GPIOD_IS_IN); -+ -+ return 0; -+} -+ -+int rk_board_late_init(void) -+{ -+ int ret; -+ -+ ret = setup_gpios(); -+ if (ret) -+ debug("Failed to configure GPIO lines: %d\n", ret); -+ -+ return ret; -+} --- -2.33.1 - diff --git a/dev-embedded/u-boot-pinephone-pro/files/1005-spl-ARM-Enable-CPU-caches.patch b/dev-embedded/u-boot-pinephone-pro/files/1005-spl-ARM-Enable-CPU-caches.patch new file mode 100644 index 0000000..04dad1c --- /dev/null +++ b/dev-embedded/u-boot-pinephone-pro/files/1005-spl-ARM-Enable-CPU-caches.patch @@ -0,0 +1,148 @@ +From 6ad822cb4d64beda76cade8761c49b55620a8b5b Mon Sep 17 00:00:00 2001 +From: Ondrej Jirman +Date: Tue, 14 Jan 2020 03:56:32 +0100 +Subject: [PATCH 29/29] spl: ARM: Enable CPU caches + +http://u-boot.10912.n7.nabble.com/RFC-PATCH-0-3-spl-Add-D-cache-support-td274750.html + +Signed-off-by: Ondrej Jirman +--- + arch/arm/lib/cache-cp15.c | 29 ++++++++++++++++++++++++ + common/spl/spl.c | 46 +++++++++++++++++++++++++++++++++++++++ + 2 files changed, 75 insertions(+) + +diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c +index aab1bf4360..c2fe0acdc4 100644 +--- a/arch/arm/lib/cache-cp15.c ++++ b/arch/arm/lib/cache-cp15.c +@@ -116,6 +116,25 @@ __weak void dram_bank_mmu_setup(int bank) + set_section_dcache(i, DCACHE_DEFAULT_OPTION); + } + ++#if defined(CONFIG_SPL_BUILD) && (defined(CONFIG_SPL_MAX_SIZE) || \ ++ defined(CONFIG_SPL_MAX_FOOTPRINT)) ++__weak void sram_bank_mmu_setup(phys_addr_t start, phys_addr_t size) ++{ ++ int i; ++ ++ for (i = start >> MMU_SECTION_SHIFT; ++ i < (start >> MMU_SECTION_SHIFT) + (size >> MMU_SECTION_SHIFT); ++ i++) ++#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH) ++ set_section_dcache(i, DCACHE_WRITETHROUGH); ++#elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC) ++ set_section_dcache(i, DCACHE_WRITEALLOC); ++#else ++ set_section_dcache(i, DCACHE_WRITEBACK); ++#endif ++} ++#endif ++ + /* to activate the MMU we need to set up virtual memory: use 1M areas */ + static inline void mmu_setup(void) + { +@@ -131,6 +150,16 @@ static inline void mmu_setup(void) + dram_bank_mmu_setup(i); + } + ++#if defined(CONFIG_SPL_BUILD) ++#if defined(CONFIG_SPL_MAX_SIZE) ++ sram_bank_mmu_setup(CONFIG_SPL_TEXT_BASE, ++ ALIGN(CONFIG_SPL_MAX_SIZE, MMU_SECTION_SIZE)); ++#elif defined(CONFIG_SPL_MAX_FOOTPRINT) ++ sram_bank_mmu_setup(CONFIG_SPL_TEXT_BASE, ++ ALIGN(CONFIG_SPL_MAX_FOOTPRINT, MMU_SECTION_SIZE)); ++#endif ++#endif ++ + #if defined(CONFIG_ARMV7_LPAE) && __LINUX_ARM_ARCH__ != 4 + /* Set up 4 PTE entries pointing to our 4 1GB page tables */ + for (i = 0; i < 4; i++) { +diff --git a/common/spl/spl.c b/common/spl/spl.c +index a0a608fd77..40c9022928 100644 +--- a/common/spl/spl.c ++++ b/common/spl/spl.c +@@ -10,6 +10,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -692,6 +693,35 @@ void board_init_f(ulong dummy) + } + #endif + ++#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) && \ ++ defined(CONFIG_ARM) ++int reserve_mmu(void) ++{ ++ phys_addr_t ram_top = 0; ++ /* reserve TLB table */ ++ gd->arch.tlb_size = PGTABLE_SIZE; ++ ++#ifdef CONFIG_SYS_SDRAM_BASE ++ ram_top = CONFIG_SYS_SDRAM_BASE; ++#endif ++ ram_top += get_effective_memsize(); ++ gd->arch.tlb_addr = ram_top - gd->arch.tlb_size; ++ debug("TLB table from %08lx to %08lx\n", gd->arch.tlb_addr, ++ gd->arch.tlb_addr + gd->arch.tlb_size); ++ return 0; ++} ++ ++__weak int dram_init_banksize(void) ++{ ++#if defined(CONFIG_NR_DRAM_BANKS) && defined(CONFIG_SYS_SDRAM_BASE) ++ gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; ++ gd->bd->bi_dram[0].size = get_effective_memsize(); ++#endif ++ return 0; ++} ++ ++#endif ++ + void board_init_r(gd_t *dummy1, ulong dummy2) + { + u32 spl_boot_list[] = { +@@ -707,6 +737,12 @@ void board_init_r(gd_t *dummy1, ulong du + debug(">>" SPL_TPL_PROMPT "board_init_r()\n"); + + spl_set_bd(); ++#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) && \ ++ defined(CONFIG_ARM) ++ dram_init_banksize(); ++ reserve_mmu(); ++ enable_caches(); ++#endif + + #if defined(CONFIG_SYS_SPL_MALLOC_START) + mem_malloc_init(CONFIG_SYS_SPL_MALLOC_START, +@@ -717,6 +753,11 @@ void board_init_r(gd_t *dummy1, ulong du + if (spl_init()) + hang(); + } ++ if (IS_ENABLED(CONFIG_SPL_ALLOC_BD) && spl_alloc_bd()) { ++ puts("Cannot alloc bd\n"); ++ hang(); ++ } ++ + #if !defined(CONFIG_PPC) && !defined(CONFIG_ARCH_MX6) + /* + * timer_init() does not exist on PPC systems. The timer is initialized +@@ -789,6 +830,11 @@ void board_init_r(gd_t *dummy1, ulong du + printf("Warning: Failed to finish bloblist (ret=%d)\n", + ret); + } ++ ++#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) && \ ++ defined(CONFIG_ARM) ++ cleanup_before_linux(); ++#endif + + switch (spl_image.os) { + case IH_OS_U_BOOT: +-- +2.31.1 + diff --git a/dev-embedded/u-boot-pinephone-pro/files/1006-common-expose-DRAM-clock-speed.patch b/dev-embedded/u-boot-pinephone-pro/files/1006-common-expose-DRAM-clock-speed.patch new file mode 100644 index 0000000..eff3a2d --- /dev/null +++ b/dev-embedded/u-boot-pinephone-pro/files/1006-common-expose-DRAM-clock-speed.patch @@ -0,0 +1,53 @@ +From a568d5efe609fec974d44fec4cba31288ab0f621 Mon Sep 17 00:00:00 2001 +From: Bobby The Builder +Date: Mon, 29 Mar 2021 16:42:07 -0400 +Subject: [PATCH 4/5] common: expose DRAM clock speed + +add memory/ram_freq +--- + common/board_f.c | 6 ++++-- + common/main.c | 7 +++++++ + 2 files changed, 11 insertions(+), 2 deletions(-) + +diff --git a/common/board_f.c b/common/board_f.c +index 0cddf0359d..e481c70ef0 100644 +--- a/common/board_f.c ++++ b/common/board_f.c +@@ -227,12 +227,14 @@ static int show_dram_config(void) + print_size(gd->bd->bi_dram[i].size, "\n"); + #endif + } +- debug("\nDRAM: "); ++ debug("\nDRAM Size: "); + + print_size(size, ""); + board_add_ram_info(0); + putc('\n'); +- ++#if defined(CONFIG_DRAM_CLK) ++ printf("DRAM Clock: %d MHz\n", CONFIG_DRAM_CLK); ++#endif + return 0; + } + +diff --git a/common/main.c b/common/main.c +index ae5bcdb32f..85adcc6c13 100644 +--- a/common/main.c ++++ b/common/main.c +@@ -46,6 +46,13 @@ void main_loop(void) + if (IS_ENABLED(CONFIG_VERSION_VARIABLE)) + env_set("ver", version_string); /* set version variable */ + ++#if defined(CONFIG_DRAM_CLK) ++ char ram_clk_string[11]; ++ sprintf(ram_clk_string, "%d", CONFIG_DRAM_CLK); ++ env_set("ram_freq", ram_clk_string); ++ printf("Set ram_freq : %s\n", ram_clk_string); ++#endif ++ + cli_init(); + + if (IS_ENABLED(CONFIG_USE_PREBOOT)) +-- +2.31.1 + diff --git a/dev-embedded/u-boot-pinephone-pro/files/1007-Improve-Allwinner-A64-timer-workaround.patch b/dev-embedded/u-boot-pinephone-pro/files/1007-Improve-Allwinner-A64-timer-workaround.patch new file mode 100644 index 0000000..e275bd5 --- /dev/null +++ b/dev-embedded/u-boot-pinephone-pro/files/1007-Improve-Allwinner-A64-timer-workaround.patch @@ -0,0 +1,11 @@ +--- u-boot-c784be467aa7d111f149c2a54557e8828bc5775a/arch/arm/cpu/armv8/generic_timer.c.orig 2021-03-10 18:44:07.000000000 +0100 ++++ u-boot-c784be467aa7d111f149c2a54557e8828bc5775a/arch/arm/cpu/armv8/generic_timer.c 2021-05-22 21:36:48.565156255 +0200 +@@ -69,7 +69,7 @@ unsigned long timer_read_counter(void) + isb(); + do { + asm volatile("mrs %0, cntpct_el0" : "=r" (cntpct)); +- } while (((cntpct + 1) & GENMASK(10, 0)) <= 1); ++ } while (((cntpct + 1) & GENMASK(8, 0)) <= 1); + + return cntpct; + } diff --git a/dev-embedded/u-boot-pinephone-pro/files/2001-mmc-sdhci-allow-disabling-sdma-in-spl.patch b/dev-embedded/u-boot-pinephone-pro/files/2001-mmc-sdhci-allow-disabling-sdma-in-spl.patch deleted file mode 100644 index ef6d9b4..0000000 --- a/dev-embedded/u-boot-pinephone-pro/files/2001-mmc-sdhci-allow-disabling-sdma-in-spl.patch +++ /dev/null @@ -1,67 +0,0 @@ -From: Peter Geis -To: Peng Fan , Jaehoon Chung -Cc: Peter Geis , u-boot@lists.denx.de -Subject: [PATCH v1 02/11] mmc: sdhci: allow disabling sdma in spl -Date: Mon, 21 Feb 2022 20:31:21 -0500 - -Rockchip emmc devices have a similar issue to Rockchip dwmmc devices, -where performing dma to sram causes errors with suspend/resume. -Allow us to toggle sdma in spl for sdhci similar to adma support, so we -can ensure dma is not used when loading the sram code. - -Signed-off-by: Peter Geis -Reviewed-by: Jaehoon Chung ---- - drivers/mmc/Kconfig | 7 +++++++ - drivers/mmc/sdhci.c | 6 +++--- - 2 files changed, 10 insertions(+), 3 deletions(-) - -diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig -index f04cc44e1973..1e4342285ce7 100644 ---- a/drivers/mmc/Kconfig -+++ b/drivers/mmc/Kconfig -@@ -468,6 +468,13 @@ config MMC_SDHCI_SDMA - This enables support for the SDMA (Single Operation DMA) defined - in the SD Host Controller Standard Specification Version 1.00 . - -+config SPL_MMC_SDHCI_SDMA -+ bool "Support SDHCI SDMA in SPL" -+ depends on MMC_SDHCI -+ help -+ This enables support for the SDMA (Single Operation DMA) defined -+ in the SD Host Controller Standard Specification Version 1.00 in SPL. -+ - config MMC_SDHCI_ADMA - bool "Support SDHCI ADMA2" - depends on MMC_SDHCI -diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c -index 766e4a6b0c5e..6285e53d12a2 100644 ---- a/drivers/mmc/sdhci.c -+++ b/drivers/mmc/sdhci.c -@@ -70,7 +70,7 @@ static void sdhci_transfer_pio(struct sdhci_host *host, struct mmc_data *data) - } - } - --#if (defined(CONFIG_MMC_SDHCI_SDMA) || CONFIG_IS_ENABLED(MMC_SDHCI_ADMA)) -+#if (CONFIG_IS_ENABLED(MMC_SDHCI_SDMA) || CONFIG_IS_ENABLED(MMC_SDHCI_ADMA)) - static void sdhci_prepare_dma(struct sdhci_host *host, struct mmc_data *data, - int *is_aligned, int trans_bytes) - { -@@ -177,7 +177,7 @@ static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data) - } - } while (!(stat & SDHCI_INT_DATA_END)); - --#if (defined(CONFIG_MMC_SDHCI_SDMA) || CONFIG_IS_ENABLED(MMC_SDHCI_ADMA)) -+#if (CONFIG_IS_ENABLED(MMC_SDHCI_SDMA) || CONFIG_IS_ENABLED(MMC_SDHCI_ADMA)) - dma_unmap_single(host->start_addr, data->blocks * data->blocksize, - mmc_get_dma_dir(data)); - #endif -@@ -836,7 +836,7 @@ int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host, - #endif - debug("%s, caps: 0x%x\n", __func__, caps); - --#ifdef CONFIG_MMC_SDHCI_SDMA -+#if CONFIG_IS_ENABLED(MMC_SDHCI_SDMA) - if ((caps & SDHCI_CAN_DO_SDMA)) { - host->flags |= USE_SDMA; - } else { diff --git a/dev-embedded/u-boot-pinephone-pro/files/3001-pinephone-pro-Remove-cargo-culted-iodomain-config.patch b/dev-embedded/u-boot-pinephone-pro/files/3001-pinephone-pro-Remove-cargo-culted-iodomain-config.patch deleted file mode 100644 index 1651216..0000000 --- a/dev-embedded/u-boot-pinephone-pro/files/3001-pinephone-pro-Remove-cargo-culted-iodomain-config.patch +++ /dev/null @@ -1,32 +0,0 @@ -From 0885f6b57b218f0de18cd67856fcfdd68843fc9a Mon Sep 17 00:00:00 2001 -From: Samuel Dionne-Riel -Date: Sun, 30 Jan 2022 21:44:07 -0500 -Subject: [PATCH 7/7] [WIP] pinephone-pro: Remove cargo-culted iodomain config - -It is unclear what it actually does, and the TRM states this register -should already be at `0x1` on reset. - -Thus it is assumed this would be redundant. Except that it is not, and -keeping this change in will break SPI NOR Flash support. The SPI bus(?) -will be tied up, I assume, and thus return `ff ff ff` as an identifier ---- - board/pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c | 3 --- - 1 file changed, 3 deletions(-) - -diff --git a/board/pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c b/board/pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c -index c51d1657a2a..22c2ced2d79 100644 ---- a/board/pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c -+++ b/board/pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c -@@ -33,9 +33,6 @@ static void setup_iodomain(void) - - /* BT565 is in 1.8v domain */ - rk_setreg(&grf->io_vsel, 1 << GRF_IO_VSEL_BT565_SHIFT); -- -- /* Set GPIO1 1.8v/3.0v source select to PMU1830_VOL */ -- rk_setreg(&pmugrf->soc_con0, 1 << PMUGRF_CON0_VSEL_SHIFT); - } - - int misc_init_r(void) --- -2.34.0 - diff --git a/dev-embedded/u-boot-pinephone-pro/files/3002-pine64-pinephonePro-SPI-support.patch b/dev-embedded/u-boot-pinephone-pro/files/3002-pine64-pinephonePro-SPI-support.patch deleted file mode 100644 index ac87d3e..0000000 --- a/dev-embedded/u-boot-pinephone-pro/files/3002-pine64-pinephonePro-SPI-support.patch +++ /dev/null @@ -1,40 +0,0 @@ -From 8945d49c2d60a3b26d215b2d6c45918ac9d143bd Mon Sep 17 00:00:00 2001 -From: Samuel Dionne-Riel -Date: Sun, 30 Jan 2022 16:59:26 -0500 -Subject: [PATCH 6/7] pine64-pinephonePro: SPI support - -NOTE: Original patch modified a bit for the used version of the PPP DT. ---- -diff --git a/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi b/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi -index 9d44db59783..28bec0a6a70 100644 ---- a/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi -+++ b/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi -@@ -42,3 +42,7 @@ - max-frequency = <20000000>; - u-boot,dm-pre-reloc; - }; -+ -+&spiflash { -+ u-boot,dm-pre-reloc; -+}; -diff --git a/arch/arm/dts/rk3399-pinephone-pro.dts b/arch/arm/dts/rk3399-pinephone-pro.dts -index e6c2df936fb..9a658f37c69 100644 ---- a/arch/arm/dts/rk3399-pinephone-pro.dts -+++ b/arch/arm/dts/rk3399-pinephone-pro.dts -@@ -503,6 +503,16 @@ - status = "okay"; - }; - -+&spi1 { -+ status = "okay"; -+ -+ spiflash: flash@0 { -+ compatible = "jedec,spi-nor"; -+ reg = <0>; -+ spi-max-frequency = <10000000>; -+ }; -+}; -+ - &vopb { - status = "okay"; - }; diff --git a/dev-embedded/u-boot-pinephone-pro/u-boot-pinephone-pro-2022.04.ebuild b/dev-embedded/u-boot-pinephone-pro/u-boot-pinephone-pro-2022.07_rc6.ebuild old mode 100644 new mode 100755 similarity index 77% rename from dev-embedded/u-boot-pinephone-pro/u-boot-pinephone-pro-2022.04.ebuild rename to dev-embedded/u-boot-pinephone-pro/u-boot-pinephone-pro-2022.07_rc6.ebuild index eb3272a..de2b854 --- a/dev-embedded/u-boot-pinephone-pro/u-boot-pinephone-pro-2022.04.ebuild +++ b/dev-embedded/u-boot-pinephone-pro/u-boot-pinephone-pro-2022.07_rc6.ebuild @@ -6,14 +6,16 @@ EAPI=8 inherit toolchain-funcs PKGREL="4" -FIRMWAREVERSION="2.6" -COMMMIT="e4b6ebd3de982ae7185dbf689a030e73fd06e0d2" +FIRMWAREVERSION="2.7.0" +CRUSTVERSION="0.5" +COMMMIT="0cc846dafcf6f6270c6587d6fe79011834d6e49a" MY_P="u-boot-${COMMMIT}" DESCRIPTION="Das U-boot and utilities for working with Das U-Boot for the PinePhone Pro" HOMEPAGE="https://www.denx.de/wiki/U-Boot/WebHome" SRC_URI=" https://source.denx.de/u-boot/u-boot/-/archive/${COMMMIT}/u-boot-${COMMMIT}.tar.gz -> u-boot-${PV}.tar.gz https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/snapshot/trusted-firmware-a-${FIRMWAREVERSION}.tar.gz + https://github.com/crust-firmware/crust/archive/refs/tags/v${CRUSTVERSION}.tar.gz " S="${WORKDIR}/${MY_P}" @@ -41,14 +43,14 @@ src_prepare() { tools/Makefile || die #Apply PinePhone Pro patches - eapply "${FILESDIR}"/0001-PPP.patch - eapply "${FILESDIR}"/1001-Correct-boot-order-to-be-USB-SD-eMMC.patch - eapply "${FILESDIR}"/1002-rockchip-Add-initial-support-for-the-PinePhone-Pro.patch - eapply "${FILESDIR}"/1004-mtd-spi-nor-ids-Add-GigaDevice-GD25LQ128E-entry.patch - eapply "${FILESDIR}"/1005-Reconfigure-GPIO4_D3-as-input-on-PinePhone-Pro.patch - eapply "${FILESDIR}"/2001-mmc-sdhci-allow-disabling-sdma-in-spl.patch - eapply "${FILESDIR}"/3001-pinephone-pro-Remove-cargo-culted-iodomain-config.patch - eapply "${FILESDIR}"/3002-pine64-pinephonePro-SPI-support.patch + eapply "${FILESDIR}"/1001-pinephone-Add-volume_key-environment-variable.patch + eapply "${FILESDIR}"/1002-Enable-led-on-boot-to-notify-user-of-boot-status.patch + eapply "${FILESDIR}"/1003-mmc-sunxi-Add-support-for-DMA-transfers.patch + eapply "${FILESDIR}"/1004-mmc-sunxi-DDR-DMA-support-for-SPL.patch + eapply "${FILESDIR}"/1005-spl-ARM-Enable-CPU-caches.patch + eapply "${FILESDIR}"/1006-common-expose-DRAM-clock-speed.patch + eapply "${FILESDIR}"/1007-Improve-Allwinner-A64-timer-workaround.patch + } @@ -57,6 +59,11 @@ src_configure() { } src_compile() { + cd ${WORKDIR}/crust-${CRUSTVERSION} + make CROSS_COMPILE=or1k-elf- pinephone_defconfig + make CROSS_COMPILE=or1k-elf- build/scp/scp.bin + cp build/scp/scp.bin ${S} + cd ${WORKDIR}/trusted-firmware-a-${FIRMWAREVERSION} unset CFLAGS CXXFLAGS CPPFLAGS LDFLAGS make PLAT=rk3399