From 1af4c86329397bc553122c650226bd5c7acb1ed0 Mon Sep 17 00:00:00 2001 From: Ondrej Jirman Date: Fri, 13 Sep 2019 22:14:43 +0200 Subject: [PATCH 28/29] mmc: sunxi: DDR/DMA support for SPL --- drivers/mmc/sunxi_mmc.c | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c index 47c947cdb8..855dfd35d9 100644 --- a/drivers/mmc/sunxi_mmc.c +++ b/drivers/mmc/sunxi_mmc.c @@ -579,7 +579,12 @@ static int sunxi_mmc_send_cmd_common(struct sunxi_mmc_priv *priv, bytecnt = data->blocksize * data->blocks; debug("trans data %d bytes\n", bytecnt); - if (bytecnt > 64 && !IS_ENABLED(SPL_BUILD)) { + // DMA doesn't work when the target is SRAM for some reason. + int reading = !!(data->flags & MMC_DATA_READ); + uint8_t* buf = (uint8_t*)(reading ? data->dest : data->src); + bool is_dram = (uintptr_t)buf >= 0x4000000; + + if (bytecnt > 64 && is_dram) { debug(" using dma %d\n", bytecnt); error = mmc_trans_data_by_dma(priv, mmc, data); writel(cmdval | cmd->cmdidx, &priv->reg->cmd); @@ -715,10 +720,19 @@ struct mmc *sunxi_mmc_init(int sdc_no) cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS; cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; + if (sdc_no == 2) + cfg->host_caps |= MMC_MODE_DDR_52MHz; cfg->f_min = 400000; cfg->f_max = 52000000; + // enough descs for a realy big u-boot (4MiB) + priv->n_dma_descs = 4*1024*1024 / DMA_BUF_MAX_SIZE; + priv->dma_descs = malloc(sizeof(struct sunxi_idma_desc) + * priv->n_dma_descs); + if (priv->dma_descs == NULL) + return NULL; + if (mmc_resource_init(sdc_no) != 0) return NULL; -- 2.31.1