From: =?utf-8?q?Kamil_Trzci=C5=84ski?= Date: Fri, 8 Jan 2021 00:19:23 +0100 Subject: [PATCH 02/36] drm: dw-mipi-dsi-rockchip: Ensure that lane is properly configured MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit ??? Signed-of-by: Kamil Trzciński --- drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c index a9acbcc..53c8b40 100644 --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c @@ -406,6 +406,14 @@ static int dw_mipi_dsi_phy_init(void *priv_data) */ vco = (dsi->lane_mbps < 200) ? 0 : (dsi->lane_mbps + 100) / 200; + if (dsi->cdata->lanecfg1_grf_reg) { + regmap_write(dsi->grf_regmap, dsi->cdata->lanecfg1_grf_reg, + dsi->cdata->lanecfg1); + + dev_info(dsi->dev, "dw_mipi_dsi_phy_init / dw_mipi_dsi_rockchip_config: %08x => set=%08x\n", + dsi->cdata->lanecfg1_grf_reg, dsi->cdata->lanecfg1); + } + i = max_mbps_to_parameter(dsi->lane_mbps); if (i < 0) { DRM_DEV_ERROR(dsi->dev,