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Droppped u-boot since tow-boot works better

This commit is contained in:
Gerben Jan Dijkman 2023-03-30 12:41:20 +02:00
parent c420720a7f
commit 51ee9aa9d7
13 changed files with 0 additions and 1637 deletions
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2
dev-embedded/u-boot-pinephone-pro/Manifest
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@ -1,2 +0,0 @@
DIST trusted-firmware-a-2.7.0.tar.gz 6511871 BLAKE2B d27be086274382bce273f3d9a04840b31577a757cfbc0cf6e767668d43177d17b392893b8fa1ddcd033312b7e39924a0997220c852fb3e1f12ed386ebc7d666a SHA512 28e46a25f0cb6de8338ad9766aa66b36df6cee2f1e732bce0cb9efcaf5f0d360a38e5ccacbfefe9b875e3ce07e825a9b2632609af48956267d10509ecfee85f6
DIST u-boot-2022.07.tar.gz 23215226 BLAKE2B 50dbe217c8c9dbe08da35260b5b831bb87b1717909c68955334d2d5188f2243be9a25c595f300598f03558d76b37adbc9ca17f55cad7791a5bac8f80412bc63d SHA512 dfd6fa530b1f3f9a6ac006e86c936a3b66e8411ec917e5d3e5775889c0464618b0ea4a3feb0a36533f24d1c73a77d6c4849b0be1e70da08dc7d7af6c0a929e87

39
dev-embedded/u-boot-pinephone-pro/files/.gitlab-ci.yml
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@ -1,39 +0,0 @@
### Generic CI Template for chrootbuild
#
#
# Usage: chrootbuild [options]
#
# -b <branch> Branch to use:
# (unstable/testing/stable-staging/stable;
# arm-unstable/arm-testing/arm-stable)
# default: unstable / arm-unstable
# -c Start with clean chroot fs
# -h This help
# -i <pkg> Install package(s) to chroot fs
# (for multiple packages repeat -i flag)
# -l <list> List(s) to build
# (for multiple lists repeat -l flag)
# -n Install built pkg to chroot fs
# -p <pkg> Package(s) to build
# (for multiple packages repeat -p flag)
# -r Remove previously built packages in $PKGDEST
# -s Sign package(s)
build-package:
tags:
# change the tag to your gitlab-runner
- bigbuilds
- aarch64
script:
# build pkg via chrootbuild
- export PKG=${PWD##*/}
- cd ..
- sudo chrootbuild -b arm-testing -cp $PKG
- mv -v ./*.pkg.tar.* $PKG
#- sudo pacman -Syy && makepkg -scr --noconfirm
artifacts:
paths:
- ./*.pkg.tar.*
expire_in: 1 week

29
dev-embedded/u-boot-pinephone-pro/files/1001-Correct-boot-order-to-be-USB-SD-eMMC.patch
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@ -1,29 +0,0 @@
From f97401137daa1cb75532c373bbcb5011f1e03585 Mon Sep 17 00:00:00 2001
From: Dan Johansen <strit@manjaro.org>
Date: Sun, 10 Oct 2021 20:19:02 +0200
Subject: [PATCH] Correct boot order to be USB -> SD -> eMMC
Signed-off-by: Dan Johansen <strit@manjaro.org>
---
include/configs/rockchip-common.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/configs/rockchip-common.h b/include/configs/rockchip-common.h
index ba7061a287..5dc92373b2 100644
--- a/include/configs/rockchip-common.h
+++ b/include/configs/rockchip-common.h
@@ -61,10 +61,10 @@
#ifdef CONFIG_ROCKCHIP_RK3399
#define BOOT_TARGET_DEVICES(func) \
+ BOOT_TARGET_USB(func) \
BOOT_TARGET_MMC(func) \
BOOT_TARGET_NVME(func) \
BOOT_TARGET_SCSI(func) \
- BOOT_TARGET_USB(func) \
BOOT_TARGET_PXE(func) \
BOOT_TARGET_DHCP(func) \
BOOT_TARGET_SF(func)
--
2.33.0

889
dev-embedded/u-boot-pinephone-pro/files/1002-rockchip-Add-initial-support-for-the-PinePhone-Pro.patch
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@ -1,889 +0,0 @@
From eea38c80ff858222e15ba4d79a0cb811adbdfc23 Mon Sep 17 00:00:00 2001
From: Martijn Braam <martijn@brixit.nl>
Date: Sat, 12 Dec 2020 13:31:03 +0100
Subject: [PATCH] rockchip: Add initial support for the PinePhone Pro
This is a new device by PINE64 that's very similar to the Pinebook Pro
that's already supported.
Specification:
- Rockchip RK3399
- 4GB Dual-Channel LPDDR4
- 128GB eMMC
- mSD card slot
- AP6255 for 802.11ac WiFi and Bluetooth
- 6 inch 720*1440 DSI display
- Quectel EG25g usb modem
- Type-C port with alt-mode display (DP 1.2) and PD charging.
Signed-off-by: Martijn Braam <martijn@brixit.nl>
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi | 44 ++
arch/arm/dts/rk3399-pinephone-pro.dts | 520 ++++++++++++++++++
arch/arm/mach-rockchip/rk3399/Kconfig | 8 +
board/pine64/pinephone-pro-rk3399/Kconfig | 15 +
board/pine64/pinephone-pro-rk3399/MAINTAINERS | 8 +
board/pine64/pinephone-pro-rk3399/Makefile | 1 +
.../pinephone-pro-rk3399.c | 57 ++
configs/pinephone-pro-rk3399_defconfig | 92 ++++
include/configs/pinephone-pro-rk3399.h | 23 +
10 files changed, 769 insertions(+)
create mode 100644 arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi
create mode 100644 arch/arm/dts/rk3399-pinephone-pro.dts
create mode 100644 board/pine64/pinephone-pro-rk3399/Kconfig
create mode 100644 board/pine64/pinephone-pro-rk3399/MAINTAINERS
create mode 100644 board/pine64/pinephone-pro-rk3399/Makefile
create mode 100644 board/pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c
create mode 100644 configs/pinephone-pro-rk3399_defconfig
create mode 100644 include/configs/pinephone-pro-rk3399.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index aeaec713..6f123425 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -145,6 +145,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \
rk3399-nanopi-r4s.dtb \
rk3399-orangepi.dtb \
rk3399-pinebook-pro.dtb \
+ rk3399-pinephone-pro.dtb \
rk3399-puma-haikou.dtb \
rk3399-roc-pc.dtb \
rk3399-roc-pc-mezzanine.dtb \
diff --git a/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi b/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi
new file mode 100644
index 00000000..9d44db59
--- /dev/null
+++ b/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Peter Robinson <pbrobinson at gmail.com>
+ * Copyright (C) 2021 Martijn Braam <martijn at brixit.nl>
+ */
+
+#include "rk3399-u-boot.dtsi"
+#include "rk3399-sdram-lpddr4-100.dtsi"
+
+/ {
+ aliases {
+ spi0 = &spi1;
+ };
+
+ chosen {
+ u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc;
+ };
+
+ config {
+ u-boot,spl-payload-offset = <0x60000>; /* @ 384KB */
+ };
+};
+
+&i2c0 {
+ u-boot,dm-pre-reloc;
+};
+
+&rk818 {
+ u-boot,dm-pre-reloc;
+};
+
+&rng {
+ status = "okay";
+};
+
+&sdhci {
+ max-frequency = <25000000>;
+ u-boot,dm-pre-reloc;
+};
+
+&sdmmc {
+ max-frequency = <20000000>;
+ u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/rk3399-pinephone-pro.dts b/arch/arm/dts/rk3399-pinephone-pro.dts
new file mode 100644
index 00000000..3fe1845c
--- /dev/null
+++ b/arch/arm/dts/rk3399-pinephone-pro.dts
@@ -0,0 +1,520 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2021 Martijn Braam <martijn@brixit.nl>
+ */
+
+/dts-v1/;
+#include "rk3399.dtsi"
+#include "rk3399-opp.dtsi"
+
+/ {
+ model = "Pine64 PinePhone Pro";
+ compatible = "pine64,pinephone-pro", "rockchip,rk3399";
+
+ chosen {
+ stdout-path = "serial2:1500000n8";
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ pinctrl-names = "default";
+ };
+
+ /* Power tree */
+ /* Root power source */
+ vcc_sysin: vcc-sysin {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_sysin";
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ /* Main 3.3v supply */
+ vcc3v3_sys: vcc3v3-sys {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc_sysin>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+};
+
+&cpu_l0 {
+ cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l1 {
+ cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l2 {
+ cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l3 {
+ cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_b0 {
+ cpu-supply = <&vdd_cpu_b>;
+};
+
+&cpu_b1 {
+ cpu-supply = <&vdd_cpu_b>;
+};
+
+&emmc_phy {
+ status = "okay";
+};
+
+&gpu {
+ mali-supply = <&vdd_gpu>;
+ status = "okay";
+};
+
+&i2c0 {
+ clock-frequency = <400000>;
+ i2c-scl-rising-time-ns = <168>;
+ i2c-scl-falling-time-ns = <4>;
+ status = "okay";
+
+ rk818: pmic@1c {
+ compatible = "rockchip,rk818";
+ reg = <0x1c>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <RK_PC5 IRQ_TYPE_LEVEL_LOW>;
+ #clock-cells = <1>;
+ clock-output-names = "xin32k", "rk808-clkout2";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_int_l>;
+ rockchip,system-power-controller;
+ wakeup-source;
+
+ vcc1-supply = <&vcc_sysin>;
+ vcc2-supply = <&vcc_sysin>;
+ vcc3-supply = <&vcc_sysin>;
+ vcc4-supply = <&vcc_sysin>;
+ vcc6-supply = <&vcc_sysin>;
+ vcc7-supply = <&vcc3v3_sys>;
+ vcc8-supply = <&vcc_sysin>;
+ vcc9-supply = <&vcc3v3_sys>;
+
+ regulators {
+ vdd_cpu_l: DCDC_REG1 {
+ regulator-name = "vdd_cpu_1";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <6001>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_center: DCDC_REG2 {
+ regulator-name = "vdd_center";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <6001>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_ddr: DCDC_REG3 {
+ regulator-name = "vcc_ddr";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vcc_1v8: DCDC_REG4 {
+ regulator-name = "vcc_1v8";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vcca3v0_codec: LDO_REG1 {
+ regulator-name = "vcca3v0_codec";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc3v0_touch: LDO_REG2 {
+ regulator-name = "vcc3v0_touch";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcca1v8_codec: LDO_REG3 {
+ regulator-name = "vcca1v8_codec";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_power_on: LDO_REG4 {
+ regulator-name = "vcc_power_on";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vcc_3v0: LDO_REG5 {
+ regulator-name = "vcc_3v0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3000000>;
+ };
+ };
+
+ vcc_1v5: LDO_REG6 {
+ regulator-name = "vcc_1v5";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1500000>;
+ };
+ };
+
+ vcc1v8_dvp: LDO_REG7 {
+ regulator-name = "vcc1v8_dvp";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc3v3_s3: LDO_REG8 {
+ regulator-name = "vcc3v3_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_sd: LDO_REG9 {
+ regulator-name = "vcc_sd";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vcc3v3_s0: SWITCH_REG {
+ regulator-name = "vcc3v3_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ boost_otg: DCDC_BOOST {
+ regulator-name = "boost_otg";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <5000000>;
+ };
+ };
+
+ otg_switch: OTG_SWITCH {
+ regulator-name = "otg_switch";
+ };
+ };
+ };
+
+ vdd_cpu_b: regulator@40 {
+ compatible = "silergy,syr827";
+ reg = <0x40>;
+ fcs,suspend-voltage-selector = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vsel1_pin>;
+ regulator-name = "vdd_cpu_b";
+ regulator-min-microvolt = <712500>;
+ regulator-max-microvolt = <1500000>;
+ regulator-ramp-delay = <1000>;
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_gpu: regulator@41 {
+ compatible = "silergy,syr828";
+ reg = <0x41>;
+ fcs,suspend-voltage-selector = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vsel2_pin>;
+ regulator-name = "vdd_gpu";
+ regulator-min-microvolt = <712500>;
+ regulator-max-microvolt = <1500000>;
+ regulator-ramp-delay = <1000>;
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+};
+
+&i2c1 {
+ i2c-scl-rising-time-ns = <300>;
+ i2c-scl-falling-time-ns = <15>;
+ status = "okay";
+};
+
+&i2c3 {
+ i2c-scl-rising-time-ns = <450>;
+ i2c-scl-falling-time-ns = <15>;
+ status = "okay";
+};
+
+&i2c4 {
+ i2c-scl-rising-time-ns = <600>;
+ i2c-scl-falling-time-ns = <20>;
+ status = "okay";
+
+ fusb0: typec-portc@22 {
+ compatible = "fcs,fusb302";
+ reg = <0x22>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <RK_PA2 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&fusb0_int>;
+ status = "okay";
+ };
+};
+
+&io_domains {
+ status = "okay";
+
+ bt656-supply = <&vcc1v8_dvp>;
+ audio-supply = <&vcca1v8_codec>;
+ sdmmc-supply = <&vcc_sd>;
+ gpio1830-supply = <&vcc_3v0>;
+};
+
+&pmu_io_domains {
+ pmu1830-supply = <&vcc_3v0>;
+ status = "okay";
+};
+
+&pinctrl {
+ bt {
+ bt_enable_h: bt-enable-h {
+ rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ bt_host_wake_l: bt-host-wake-l {
+ rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_down>;
+ };
+
+ bt_wake_l: bt-wake-l {
+ rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ buttons {
+ pwrbtn: pwrbtn {
+ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ fusb302x {
+ fusb0_int: fusb0-int {
+ rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ leds {
+ work_led_pin: work-led-pin {
+ rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ diy_led_pin: diy-led-pin {
+ rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ pcie {
+ pcie_perst: pcie-perst {
+ rockchip,pins = <2 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ pcie_pwr_en: pcie-pwr-en {
+ rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ pmic {
+ pmic_int_l: pmic-int-l {
+ rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+
+ vsel1_pin: vsel1-pin {
+ rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>;
+ };
+
+ vsel2_pin: vsel2-pin {
+ rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
+ };
+ };
+
+ sdcard {
+ sdmmc0_pwr_h: sdmmc0-pwr-h {
+ rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ };
+
+ sdio-pwrseq {
+ wifi_enable_h: wifi-enable-h {
+ rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ usb-typec {
+ vcc5v0_typec_en: vcc5v0_typec_en {
+ rockchip,pins = <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ usb2 {
+ vcc5v0_host_en: vcc5v0-host-en {
+ rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
+&pwm0 {
+ status = "okay";
+};
+
+&pwm1 {
+ status = "okay";
+};
+
+&pwm2 {
+ status = "okay";
+};
+
+&sdio0 {
+ bus-width = <4>;
+ cap-sd-highspeed;
+ cap-sdio-irq;
+ disable-wp;
+ keep-power-in-suspend;
+ mmc-pwrseq = <&sdio_pwrseq>;
+ non-removable;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
+ sd-uhs-sdr104;
+ status = "okay";
+};
+
+&sdmmc {
+ bus-width = <4>;
+ cap-sd-highspeed;
+ cd-gpios = <&gpio0 7 GPIO_ACTIVE_LOW>;
+ disable-wp;
+ max-frequency = <150000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;
+ vmmc-supply = <&vcc3v3_s3>;
+ vqmmc-supply = <&vcc_1v8>;
+ status = "okay";
+};
+
+&sdhci {
+ bus-width = <8>;
+ mmc-hs200-1_8v;
+ non-removable;
+ status = "okay";
+};
+
+&tsadc {
+ /* tshut mode 0:CRU 1:GPIO */
+ rockchip,hw-tshut-mode = <1>;
+ /* tshut polarity 0:LOW 1:HIGH */
+ rockchip,hw-tshut-polarity = <1>;
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&vopb {
+ status = "okay";
+};
+
+&vopb_mmu {
+ status = "okay";
+};
+
+&vopl {
+ status = "okay";
+};
+
+&vopl_mmu {
+ status = "okay";
+};
diff --git a/arch/arm/mach-rockchip/rk3399/Kconfig b/arch/arm/mach-rockchip/rk3399/Kconfig
index 17628f91..3ba603ca 100644
--- a/arch/arm/mach-rockchip/rk3399/Kconfig
+++ b/arch/arm/mach-rockchip/rk3399/Kconfig
@@ -28,6 +28,13 @@ config TARGET_PINEBOOK_PRO_RK3399
with 4Gb RAM, onboard eMMC, USB-C, a USB3 and USB2 port,
1920*1080 screen and all the usual laptop features.
+config TARGET_PINEPHONE_PRO_RK3399
+ bool "PinePhone Pro"
+ help
+ PinePhone Pro is a phone based on the Rockchip rk3399 SoC
+ with 4Gb RAM, onboard eMMC, USB-C, a headphone jack,
+ 720x1440 screen and an external Quectel USB modem.
+
config TARGET_PUMA_RK3399
bool "Theobroma Systems RK3399-Q7 (Puma)"
help
@@ -154,6 +161,7 @@ endif # BOOTCOUNT_LIMIT
source "board/firefly/roc-pc-rk3399/Kconfig"
source "board/google/gru/Kconfig"
source "board/pine64/pinebook-pro-rk3399/Kconfig"
+source "board/pine64/pinephone-pro-rk3399/Kconfig"
source "board/pine64/rockpro64_rk3399/Kconfig"
source "board/rockchip/evb_rk3399/Kconfig"
source "board/theobroma-systems/puma_rk3399/Kconfig"
diff --git a/board/pine64/pinephone-pro-rk3399/Kconfig b/board/pine64/pinephone-pro-rk3399/Kconfig
new file mode 100644
index 00000000..13d6465a
--- /dev/null
+++ b/board/pine64/pinephone-pro-rk3399/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_PINEPHONE_PRO_RK3399
+
+config SYS_BOARD
+ default "pinephone-pro-rk3399"
+
+config SYS_VENDOR
+ default "pine64"
+
+config SYS_CONFIG_NAME
+ default "pinephone-pro-rk3399"
+
+config BOARD_SPECIFIC_OPTIONS
+ def_bool y
+
+endif
diff --git a/board/pine64/pinephone-pro-rk3399/MAINTAINERS b/board/pine64/pinephone-pro-rk3399/MAINTAINERS
new file mode 100644
index 00000000..9ca4fc4c
--- /dev/null
+++ b/board/pine64/pinephone-pro-rk3399/MAINTAINERS
@@ -0,0 +1,8 @@
+PINEPHONE_PRO
+M: Martijn Braam <martijn@brixit.nl>
+S: Maintained
+F: board/pine64/rk3399-pinephone-pro/
+F: include/configs/rk3399-pinephone-pro.h
+F: arch/arm/dts/rk3399-pinephone-pro.dts
+F: arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi
+F: configs/pinephone-pro-rk3399_defconfig
diff --git a/board/pine64/pinephone-pro-rk3399/Makefile b/board/pine64/pinephone-pro-rk3399/Makefile
new file mode 100644
index 00000000..8d920305
--- /dev/null
+++ b/board/pine64/pinephone-pro-rk3399/Makefile
@@ -0,0 +1 @@
+obj-y += pinephone-pro-rk3399.o
diff --git a/board/pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c b/board/pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c
new file mode 100644
index 00000000..8efeb6ea
--- /dev/null
+++ b/board/pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c
@@ -0,0 +1,57 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2019 Vasily Khoruzhick <anarsoul@gmail.com>
+ * (C) Copyright 2021 Martijn Braam <martijn@brixit.nl>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <init.h>
+#include <syscon.h>
+#include <asm/io.h>
+#include <asm/arch-rockchip/clock.h>
+#include <asm/arch-rockchip/grf_rk3399.h>
+#include <asm/arch-rockchip/hardware.h>
+#include <asm/arch-rockchip/misc.h>
+
+#define GRF_IO_VSEL_BT565_SHIFT 0
+#define PMUGRF_CON0_VSEL_SHIFT 8
+
+#ifdef CONFIG_MISC_INIT_R
+static void setup_iodomain(void)
+{
+ struct rk3399_grf_regs *grf =
+ syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+ struct rk3399_pmugrf_regs *pmugrf =
+ syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
+
+ /* BT565 is in 1.8v domain */
+ rk_setreg(&grf->io_vsel, 1 << GRF_IO_VSEL_BT565_SHIFT);
+
+ /* Set GPIO1 1.8v/3.0v source select to PMU1830_VOL */
+ rk_setreg(&pmugrf->soc_con0, 1 << PMUGRF_CON0_VSEL_SHIFT);
+}
+
+int misc_init_r(void)
+{
+ const u32 cpuid_offset = 0x7;
+ const u32 cpuid_length = 0x10;
+ u8 cpuid[cpuid_length];
+ int ret;
+
+ setup_iodomain();
+
+ ret = rockchip_cpuid_from_efuse(cpuid_offset, cpuid_length, cpuid);
+ if (ret)
+ return ret;
+
+ ret = rockchip_cpuid_set(cpuid, cpuid_length);
+ if (ret)
+ return ret;
+
+ ret = rockchip_setup_macaddr();
+
+ return ret;
+}
+
+#endif
diff --git a/configs/pinephone-pro-rk3399_defconfig b/configs/pinephone-pro-rk3399_defconfig
new file mode 100644
index 00000000..2cf80f7d
--- /dev/null
+++ b/configs/pinephone-pro-rk3399_defconfig
@@ -0,0 +1,92 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SYS_TEXT_BASE=0x00200000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x8000
+CONFIG_ROCKCHIP_RK3399=y
+CONFIG_TARGET_PINEPHONE_PRO_RK3399=y
+CONFIG_DEBUG_UART_BASE=0xFF1A0000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_DEFAULT_DEVICE_TREE="rk3399-pinephone-pro"
+CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0x800800
+CONFIG_BOOTDELAY=3
+CONFIG_USE_PREBOOT=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-pinephone-pro.dtb"
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_MISC_INIT_R=y
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
+CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_TPL=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TIME=y
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_DM_KEYBOARD=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_MISC=y
+CONFIG_ROCKCHIP_EFUSE=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_SF_DEFAULT_SPEED=20000000
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_DM_ETH=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_TYPEC=y
+CONFIG_DM_PMIC_FAN53555=y
+CONFIG_PMIC_RK8XX=y
+CONFIG_REGULATOR_PWM=y
+CONFIG_REGULATOR_RK8XX=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_RAM_RK3399_LPDDR4=y
+CONFIG_DM_RESET=y
+CONFIG_DM_RNG=y
+CONFIG_RNG_ROCKCHIP=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_ROCKCHIP_SPI=y
+CONFIG_SYSRESET=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_GENERIC=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_RTL8152=y
+CONFIG_DM_VIDEO=y
+CONFIG_DISPLAY=y
+CONFIG_VIDEO_ROCKCHIP=y
+CONFIG_DISPLAY_ROCKCHIP_EDP=y
+CONFIG_SPL_TINY_MEMSET=y
+CONFIG_ERRNO_STR=y
diff --git a/include/configs/pinephone-pro-rk3399.h b/include/configs/pinephone-pro-rk3399.h
new file mode 100644
index 00000000..fefa793f
--- /dev/null
+++ b/include/configs/pinephone-pro-rk3399.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016 Rockchip Electronics Co., Ltd
+ * Copyright (C) 2020 Peter Robinson <pbrobinson at gmail.com>
+ * Copyright (C) 2021 Martijn Braam <martijn@brixit.nl>
+ */
+
+#ifndef __PINEPHONE_PRO_RK3399_H
+#define __PINEPHONE_PRO_RK3399_H
+
+#define ROCKCHIP_DEVICE_SETTINGS \
+ "stdin=serial,usbkbd\0" \
+ "stdout=serial,vidconsole\0" \
+ "stderr=serial,vidconsole\0"
+
+#include <configs/rk3399_common.h>
+
+#define SDRAM_BANK_SIZE (2UL << 30)
+
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
+
+#endif
--
2.34.1

228
dev-embedded/u-boot-pinephone-pro/files/1003-Configure-USB-power-settings-for-PinePhone-Pro.patch
View File

@ -1,228 +0,0 @@
From 8ee2257dda6bed2f1ae117e614637036003785d4 Mon Sep 17 00:00:00 2001
From: Dragan Simic <dragan.simic@gmail.com>
Date: Thu, 30 Dec 2021 00:08:51 +0100
Subject: [PATCH] Configure USB power settings for PinePhone Pro
---
arch/arm/mach-rockchip/rk3399/rk3399.c | 5 ++
.../pinephone-pro-rk3399.c | 58 ++++++++++++++++---
configs/pinephone-pro-rk3399_defconfig | 6 ++
drivers/power/regulator/rk8xx.c | 21 ++++---
4 files changed, 72 insertions(+), 18 deletions(-)
diff --git a/arch/arm/mach-rockchip/rk3399/rk3399.c b/arch/arm/mach-rockchip/rk3399/rk3399.c
index d40969c8..644e4ab2 100644
--- a/arch/arm/mach-rockchip/rk3399/rk3399.c
+++ b/arch/arm/mach-rockchip/rk3399/rk3399.c
@@ -248,9 +248,14 @@ void __weak led_setup(void)
{
}
+void __weak power_setup(void)
+{
+}
+
void spl_board_init(void)
{
led_setup();
+ power_setup();
#if defined(SPL_GPIO)
struct rockchip_cru *cru = rockchip_get_cru();
diff --git a/board/pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c b/board/pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c
index 8efeb6ea..88583e31 100644
--- a/board/pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c
+++ b/board/pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c
@@ -2,8 +2,14 @@
/*
* (C) Copyright 2019 Vasily Khoruzhick <anarsoul@gmail.com>
* (C) Copyright 2021 Martijn Braam <martijn@brixit.nl>
+ * (C) Copyright 2021 Dragan Simic <dsimic@buserror.io>
*/
+/*
+ * TODO: Disable debugging
+ */
+#define DEBUG
+
#include <common.h>
#include <dm.h>
#include <init.h>
@@ -13,6 +19,8 @@
#include <asm/arch-rockchip/grf_rk3399.h>
#include <asm/arch-rockchip/hardware.h>
#include <asm/arch-rockchip/misc.h>
+#include <power/regulator.h>
+#include <power/rk8xx_pmic.h>
#define GRF_IO_VSEL_BT565_SHIFT 0
#define PMUGRF_CON0_VSEL_SHIFT 8
@@ -20,15 +28,13 @@
#ifdef CONFIG_MISC_INIT_R
static void setup_iodomain(void)
{
- struct rk3399_grf_regs *grf =
- syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
- struct rk3399_pmugrf_regs *pmugrf =
- syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
+ struct rk3399_grf_regs *grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+ struct rk3399_pmugrf_regs *pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
- /* BT565 is in 1.8v domain */
+ /* BT565 is in 1.8 V domain */
rk_setreg(&grf->io_vsel, 1 << GRF_IO_VSEL_BT565_SHIFT);
- /* Set GPIO1 1.8v/3.0v source select to PMU1830_VOL */
+ /* Set GPIO1 1.8/3.0 V source select to PMU1830_VOL */
rk_setreg(&pmugrf->soc_con0, 1 << PMUGRF_CON0_VSEL_SHIFT);
}
@@ -53,5 +59,43 @@ int misc_init_r(void)
return ret;
}
+#endif /* CONFIG_MISC_INIT_R */
-#endif
+/*
+ * TODO: Change CONFIG_SPL_POWER_SUPPORT to CONFIG_SPL_POWER, to match newer U-Boot versions.
+ * The same applies to CONFIG_SPL_I2C_SUPPORT.
+ */
+
+#if defined(CONFIG_SPL_BUILD) && \
+ CONFIG_IS_ENABLED(POWER_SUPPORT) && !CONFIG_IS_ENABLED(OF_PLATDATA)
+static int setup_usb_power(void)
+{
+ struct udevice *pmic;
+ int ret;
+
+ ret = uclass_first_device_err(UCLASS_PMIC, &pmic);
+ if (ret)
+ return ret;
+
+ /* set USB current limit to 2.5 A */
+ ret = rk818_spl_configure_usb_input_current(pmic, 2500);
+ if (ret)
+ return ret;
+
+ /* set USB low voltage threshold to 3.26 V */
+ ret = rk818_spl_configure_usb_chrg_shutdown(pmic, 3260000);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+void power_setup(void)
+{
+ int ret;
+
+ ret = setup_usb_power();
+ if (ret)
+ debug("Failed to configure USB power settings: %d\n", ret);
+}
+#endif /* CONFIG_SPL_BUILD && POWER_SUPPORT && !OF_PLATDATA */
diff --git a/configs/pinephone-pro-rk3399_defconfig b/configs/pinephone-pro-rk3399_defconfig
index 2cf80f7d..b7ca9317 100644
--- a/configs/pinephone-pro-rk3399_defconfig
+++ b/configs/pinephone-pro-rk3399_defconfig
@@ -23,6 +23,11 @@ CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
CONFIG_SPL_MTD_SUPPORT=y
CONFIG_SPL_SPI_LOAD=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_POWER_SUPPORT=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_REGULATOR=y
CONFIG_TPL=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPIO=y
@@ -34,6 +39,7 @@ CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TIME=y
CONFIG_CMD_PMIC=y
+# CONFIG_SPL_PMIC_CHILDREN is not set
CONFIG_CMD_REGULATOR=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
diff --git a/drivers/power/regulator/rk8xx.c b/drivers/power/regulator/rk8xx.c
index 0ee07ad2..9d42a6ca 100644
--- a/drivers/power/regulator/rk8xx.c
+++ b/drivers/power/regulator/rk8xx.c
@@ -16,14 +16,10 @@
#include <power/pmic.h>
#include <power/regulator.h>
-#ifndef CONFIG_SPL_BUILD
-#define ENABLE_DRIVER
-#endif
-
/* Not used or exisit register and configure */
#define NA 0xff
-/* Field Definitions */
+/* Field definitions */
#define RK808_BUCK_VSEL_MASK 0x3f
#define RK808_BUCK4_VSEL_MASK 0xf
#define RK808_LDO_VSEL_MASK 0x1f
@@ -145,7 +141,7 @@ static const struct rk8xx_reg_info rk818_buck[] = {
{ 1800000, 100000, REG_BUCK4_ON_VSEL, REG_BUCK4_SLP_VSEL, REG_BUCK4_CONFIG, RK818_BUCK4_VSEL_MASK, },
};
-#ifdef ENABLE_DRIVER
+#if CONFIG_IS_ENABLED(PMIC_CHILDREN)
static const struct rk8xx_reg_info rk808_ldo[] = {
{ 1800000, 100000, REG_LDO1_ON_VSEL, REG_LDO1_SLP_VSEL, NA, RK808_LDO_VSEL_MASK, },
{ 1800000, 100000, REG_LDO2_ON_VSEL, REG_LDO2_SLP_VSEL, NA, RK808_LDO_VSEL_MASK, },
@@ -206,8 +202,9 @@ static const struct rk8xx_reg_info rk818_ldo[] = {
{ 800000, 100000, REG_LDO7_ON_VSEL, REG_LDO7_SLP_VSEL, NA, RK818_LDO_VSEL_MASK, },
{ 1800000, 100000, REG_LDO8_ON_VSEL, REG_LDO8_SLP_VSEL, NA, RK818_LDO_VSEL_MASK, },
};
-#endif
+#endif /* PMIC_CHILDREN */
+#ifdef CONFIG_SPL_BUILD
static const u16 rk818_chrg_cur_input_array[] = {
450, 800, 850, 1000, 1250, 1500, 1750, 2000, 2250, 2500, 2750, 3000
};
@@ -215,6 +212,7 @@ static const u16 rk818_chrg_cur_input_array[] = {
static const uint rk818_chrg_shutdown_vsel_array[] = {
2780000, 2850000, 2920000, 2990000, 3060000, 3130000, 3190000, 3260000
};
+#endif /* CONFIG_SPL_BUILD */
static const struct rk8xx_reg_info *get_buck_reg(struct udevice *pmic,
int num, int uvolt)
@@ -357,7 +355,7 @@ static int _buck_set_enable(struct udevice *pmic, int buck, bool enable)
return ret;
}
-#ifdef ENABLE_DRIVER
+#if CONFIG_IS_ENABLED(PMIC_CHILDREN)
static int _buck_set_suspend_value(struct udevice *pmic, int buck, int uvolt)
{
const struct rk8xx_reg_info *info = get_buck_reg(pmic, buck, uvolt);
@@ -1121,8 +1119,9 @@ U_BOOT_DRIVER(rk8xx_switch) = {
.ops = &rk8xx_switch_ops,
.probe = rk8xx_switch_probe,
};
-#endif
+#endif /* PMIC_CHILDREN */
+#ifdef CONFIG_SPL_BUILD
int rk8xx_spl_configure_buck(struct udevice *pmic, int buck, int uvolt)
{
int ret;
@@ -1153,6 +1152,6 @@ int rk818_spl_configure_usb_chrg_shutdown(struct udevice *pmic, int uvolt)
if (uvolt <= rk818_chrg_shutdown_vsel_array[i])
break;
- return pmic_clrsetbits(pmic, REG_USB_CTRL, RK818_USB_CHG_SD_VSEL_MASK,
- i);
+ return pmic_clrsetbits(pmic, REG_USB_CTRL, RK818_USB_CHG_SD_VSEL_MASK, i);
}
+#endif /* CONFIG_SPL_BUILD */
--
2.34.1

28
dev-embedded/u-boot-pinephone-pro/files/1004-mtd-spi-nor-ids-Add-GigaDevice-GD25LQ128E-entry.patch
View File

@ -1,28 +0,0 @@
From 679d7562f4711b1ad8c5ea54aa804fde5da5a19d Mon Sep 17 00:00:00 2001
From: Samuel Dionne-Riel <samuel@dionne-riel.com>
Date: Sat, 5 Feb 2022 21:00:53 -0500
Subject: [PATCH] mtd: spi-nor-ids: Add GigaDevice GD25LQ128E entry
---
drivers/mtd/spi/spi-nor-ids.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
index 4aef1ddd6e2..ff5bc2b2d78 100644
--- a/drivers/mtd/spi/spi-nor-ids.c
+++ b/drivers/mtd/spi/spi-nor-ids.c
@@ -112,6 +112,11 @@ const struct flash_info spi_nor_ids[] = {
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
},
+ {
+ INFO("gd25lq128e", 0x257018, 0, 64 * 1024, 256,
+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
+ SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
+ },
{
INFO("gd25q128", 0xc84018, 0, 64 * 1024, 256,
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
--
2.34.0

67
dev-embedded/u-boot-pinephone-pro/files/1005-Reconfigure-GPIO4_D3-as-input-on-PinePhone-Pro.patch
View File

@ -1,67 +0,0 @@
From 7d114ec31e537fcb4c2e4f0fca867b050fd59549 Mon Sep 17 00:00:00 2001
From: Dragan Simic <dragan.simic@gmail.com>
Date: Thu, 10 Feb 2022 14:43:05 +0100
Subject: [PATCH] Reconfigure GPIO4_D3 as input on PinePhone Pro
---
.../pinephone-pro-rk3399.c | 39 ++++++++++++++++++-
1 file changed, 38 insertions(+), 1 deletion(-)
diff --git a/board/pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c b/board/pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c
index d79084614f..bc19b275b2 100644
--- a/board/pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c
+++ b/board/pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c
@@ -12,6 +12,7 @@
#include <asm/arch-rockchip/grf_rk3399.h>
#include <asm/arch-rockchip/hardware.h>
#include <asm/arch-rockchip/misc.h>
+#include <asm-generic/gpio.h>
#define GRF_IO_VSEL_BT565_SHIFT 0
#define PMUGRF_CON0_VSEL_SHIFT 8
@@ -52,5 +53,41 @@ int misc_init_r(void)
return ret;
}
-
#endif
+
+#define GPIO4_D3 "155"
+
+static int setup_gpios(void)
+{
+ struct gpio_desc gpio;
+ int ret;
+
+ /*
+ * MaskROM enables output on GPIO4_D3 and leaves it that way, seemingly
+ * because the RK3399 reference BOX and VR REF designs use GPIO4_D3 as
+ * EFUSE_VQPS (AD23) power control output, while it is a light sensor
+ * interrupt on the PinePhone Pro and needs to be configured as input.
+ */
+ ret = dm_gpio_lookup_name(GPIO4_D3, &gpio);
+ if (ret)
+ return ret;
+
+ ret = dm_gpio_request(&gpio, "light_int_l");
+ if (ret)
+ return ret;
+
+ dm_gpio_set_dir_flags(&gpio, GPIOD_IS_IN);
+
+ return 0;
+}
+
+int rk_board_late_init(void)
+{
+ int ret;
+
+ ret = setup_gpios();
+ if (ret)
+ debug("Failed to configure GPIO lines: %d\n", ret);
+
+ return ret;
+}
--
2.33.1

67
dev-embedded/u-boot-pinephone-pro/files/2001-mmc-sdhci-allow-disabling-sdma-in-spl.patch
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@ -1,67 +0,0 @@
From: Peter Geis <pgwipeout@gmail.com>
To: Peng Fan <peng.fan@nxp.com>, Jaehoon Chung <jh80.chung@samsung.com>
Cc: Peter Geis <pgwipeout@gmail.com>, u-boot@lists.denx.de
Subject: [PATCH v1 02/11] mmc: sdhci: allow disabling sdma in spl
Date: Mon, 21 Feb 2022 20:31:21 -0500
Rockchip emmc devices have a similar issue to Rockchip dwmmc devices,
where performing dma to sram causes errors with suspend/resume.
Allow us to toggle sdma in spl for sdhci similar to adma support, so we
can ensure dma is not used when loading the sram code.
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
---
drivers/mmc/Kconfig | 7 +++++++
drivers/mmc/sdhci.c | 6 +++---
2 files changed, 10 insertions(+), 3 deletions(-)
diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index f04cc44e1973..1e4342285ce7 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -468,6 +468,13 @@ config MMC_SDHCI_SDMA
This enables support for the SDMA (Single Operation DMA) defined
in the SD Host Controller Standard Specification Version 1.00 .
+config SPL_MMC_SDHCI_SDMA
+ bool "Support SDHCI SDMA in SPL"
+ depends on MMC_SDHCI
+ help
+ This enables support for the SDMA (Single Operation DMA) defined
+ in the SD Host Controller Standard Specification Version 1.00 in SPL.
+
config MMC_SDHCI_ADMA
bool "Support SDHCI ADMA2"
depends on MMC_SDHCI
diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c
index 766e4a6b0c5e..6285e53d12a2 100644
--- a/drivers/mmc/sdhci.c
+++ b/drivers/mmc/sdhci.c
@@ -70,7 +70,7 @@ static void sdhci_transfer_pio(struct sdhci_host *host, struct mmc_data *data)
}
}
-#if (defined(CONFIG_MMC_SDHCI_SDMA) || CONFIG_IS_ENABLED(MMC_SDHCI_ADMA))
+#if (CONFIG_IS_ENABLED(MMC_SDHCI_SDMA) || CONFIG_IS_ENABLED(MMC_SDHCI_ADMA))
static void sdhci_prepare_dma(struct sdhci_host *host, struct mmc_data *data,
int *is_aligned, int trans_bytes)
{
@@ -177,7 +177,7 @@ static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data)
}
} while (!(stat & SDHCI_INT_DATA_END));
-#if (defined(CONFIG_MMC_SDHCI_SDMA) || CONFIG_IS_ENABLED(MMC_SDHCI_ADMA))
+#if (CONFIG_IS_ENABLED(MMC_SDHCI_SDMA) || CONFIG_IS_ENABLED(MMC_SDHCI_ADMA))
dma_unmap_single(host->start_addr, data->blocks * data->blocksize,
mmc_get_dma_dir(data));
#endif
@@ -836,7 +836,7 @@ int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host,
#endif
debug("%s, caps: 0x%x\n", __func__, caps);
-#ifdef CONFIG_MMC_SDHCI_SDMA
+#if CONFIG_IS_ENABLED(MMC_SDHCI_SDMA)
if ((caps & SDHCI_CAN_DO_SDMA)) {
host->flags |= USE_SDMA;
} else {

32
dev-embedded/u-boot-pinephone-pro/files/3001-pinephone-pro-Remove-cargo-culted-iodomain-config.patch
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@ -1,32 +0,0 @@
From 0885f6b57b218f0de18cd67856fcfdd68843fc9a Mon Sep 17 00:00:00 2001
From: Samuel Dionne-Riel <samuel@dionne-riel.com>
Date: Sun, 30 Jan 2022 21:44:07 -0500
Subject: [PATCH 7/7] [WIP] pinephone-pro: Remove cargo-culted iodomain config
It is unclear what it actually does, and the TRM states this register
should already be at `0x1` on reset.
Thus it is assumed this would be redundant. Except that it is not, and
keeping this change in will break SPI NOR Flash support. The SPI bus(?)
will be tied up, I assume, and thus return `ff ff ff` as an identifier
---
board/pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/board/pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c b/board/pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c
index c51d1657a2a..22c2ced2d79 100644
--- a/board/pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c
+++ b/board/pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c
@@ -33,9 +33,6 @@ static void setup_iodomain(void)
/* BT565 is in 1.8v domain */
rk_setreg(&grf->io_vsel, 1 << GRF_IO_VSEL_BT565_SHIFT);
-
- /* Set GPIO1 1.8v/3.0v source select to PMU1830_VOL */
- rk_setreg(&pmugrf->soc_con0, 1 << PMUGRF_CON0_VSEL_SHIFT);
}
int misc_init_r(void)
--
2.34.0

40
dev-embedded/u-boot-pinephone-pro/files/3002-pine64-pinephonePro-SPI-support.patch
View File

@ -1,40 +0,0 @@
From 8945d49c2d60a3b26d215b2d6c45918ac9d143bd Mon Sep 17 00:00:00 2001
From: Samuel Dionne-Riel <samuel@dionne-riel.com>
Date: Sun, 30 Jan 2022 16:59:26 -0500
Subject: [PATCH 6/7] pine64-pinephonePro: SPI support
NOTE: Original patch modified a bit for the used version of the PPP DT.
---
diff --git a/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi b/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi
index 9d44db59783..28bec0a6a70 100644
--- a/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi
+++ b/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi
@@ -42,3 +42,7 @@
max-frequency = <20000000>;
u-boot,dm-pre-reloc;
};
+
+&spiflash {
+ u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/rk3399-pinephone-pro.dts b/arch/arm/dts/rk3399-pinephone-pro.dts
index e6c2df936fb..9a658f37c69 100644
--- a/arch/arm/dts/rk3399-pinephone-pro.dts
+++ b/arch/arm/dts/rk3399-pinephone-pro.dts
@@ -503,6 +503,16 @@
status = "okay";
};
+&spi1 {
+ status = "okay";
+
+ spiflash: flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <10000000>;
+ };
+};
+
&vopb {
status = "okay";
};

36
dev-embedded/u-boot-pinephone-pro/files/boot.txt
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@ -1,36 +0,0 @@
#
# /boot/boot.txt
# After modifying, run "ppp-uboot-mkscr" to re-generate the U-Boot boot script.
#
#
# This is the description of the GPIO lines used in this boot script:
#
# GPIO #105 is GPIO3_B1, or RK3399 ball C27, which controls the vibrator motor
# GPIO #154 is GPIO4_D2, or RK3399 ball AH3, which controls the red part of the multicolor LED
# GPIO #157 is GPIO4_D5, or RK3399 ball AJ3, which controls the green part of the multicolor LED
# GPIO #158 is GPIO4_D6, or RK3399 ball AG4, which controls the blue part of the multicolor LED
#
gpio set 105
gpio set 154
# Set root partition to the second partition of boot device
uuid_boot=""
uuid_root=""
setenv bootargs loglevel=4 console=ttyS2,1500000 console=tty0 earlycon=uart8250,mmio32,0xff1a0000 consoleblank=0 boot=PARTUUID=${uuid_boot} root=PARTUUID=${uuid_root} rw rootwait quiet audit=0 bootsplash.bootfile=bootsplash-themes/manjaro/bootsplash
if load ${devtype} ${devnum}:${distro_bootpart} ${kernel_addr_r} /Image; then
gpio clear 105
if load ${devtype} ${devnum}:${distro_bootpart} ${fdt_addr_r} /dtbs/${fdtfile}; then
if load ${devtype} ${devnum}:${distro_bootpart} ${ramdisk_addr_r} /initramfs-linux.img; then
gpio set 157
booti ${kernel_addr_r} ${ramdisk_addr_r}:${filesize} ${fdt_addr_r};
else
gpio set 158
booti ${kernel_addr_r} - ${fdt_addr_r};
fi;
fi;
fi
# EOF

66
dev-embedded/u-boot-pinephone-pro/files/ppp-uboot-mkscr
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@ -1,66 +0,0 @@
#!/bin/bash
#
# /usr/bin/ppp-uboot-mkscr
# Utility that generates the U-Boot boot script.
#
# Source and destination file paths
BOOT_TXT="/boot/boot.txt"
BOOT_SCR="/boot/boot.scr"
# Boot script description
IMAGE_DESC="U-Boot boot script"
# Determine the performed action
if [[ ! -r ${BOOT_SCR} ]]; then
ACTION="Generating"
else
ACTION="Re-generating"
fi
# Check that we're running as root
if [[ ${EUID} != 0 ]]; then
echo "${ACTION} ${IMAGE_DESC} not possible, please execute this utility as root."
exit 1
fi
# Make sure that the required utility is available
if [[ ! -x /usr/bin/mkimage ]]; then
echo "${ACTION} ${IMAGE_DESC} not possible, mkimage utility not found."
echo "Please emerge the u-boot-tools package, by running the following command:"
echo " emerge dev-embedded/u-boot-tools"
exit 1
fi
# Check that the source file exists
if [[ ! -r ${BOOT_TXT} ]]; then
echo "${ACTION} ${IMAGE_DESC} not possible, file ${BOOT_TXT} not found."
echo "Please emerge the u-boot-pinephone-pro package, by running the following command:"
echo " emerge dev-embedded/u-boot-pinephone-pro"
exit 1
fi
# Is this a quiet execution?
VERBOSE=true
while getopts "q" SWITCH; do
if [[ ${SWITCH} = "q" ]]; then
VERBOSE=false
fi
done
# Generate the U-Boot boot script
echo "${ACTION} ${IMAGE_DESC} ${BOOT_SCR}..."
if [[ ${VERBOSE} = true ]]; then
mkimage -A arm -O linux -T script -C none -n "${IMAGE_DESC}" -d ${BOOT_TXT} ${BOOT_SCR}
else
mkimage -A arm -O linux -T script -C none -n "${IMAGE_DESC}" -d ${BOOT_TXT} ${BOOT_SCR} > /dev/null 2>&1
if [[ $? = 0 ]]; then
echo "${ACTION} ${IMAGE_DESC} from ${BOOT_TXT} completed successfully."
else
echo "${ACTION} ${IMAGE_DESC} from ${BOOT_TXT} failed due to unknown reason."
echo "Please try generating the boot script again, or your phone may no longer boot properly."
fi
fi
# EOF

114
dev-embedded/u-boot-pinephone-pro/u-boot-pinephone-pro-2022.07.ebuild
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@ -1,114 +0,0 @@
# Copyright 1999-2022 Gentoo Authors
# Distributed under the terms of the GNU General Public License v2
EAPI=8
inherit toolchain-funcs
PKGREL="4"
FIRMWAREVERSION="2.7.0"
COMMMIT="e092e3250270a1016c877da7bdd9384f14b1321e"
MY_P="u-boot-${COMMMIT}"
DESCRIPTION="Das U-boot and utilities for working with Das U-Boot for the PinePhone Pro"
HOMEPAGE="https://www.denx.de/wiki/U-Boot/WebHome"
SRC_URI="
https://source.denx.de/u-boot/u-boot/-/archive/${COMMMIT}/u-boot-${COMMMIT}.tar.gz -> u-boot-${PV}.tar.gz
https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/snapshot/trusted-firmware-a-${FIRMWAREVERSION}.tar.gz
"
S="${WORKDIR}/${MY_P}"
LICENSE="GPL-2"
SLOT="0"
KEYWORDS="~arm64"
RDEPEND="dev-libs/openssl:="
DEPEND="${RDEPEND}"
BDEPEND="
sys-apps/dtc
sys-devel/bison
sys-devel/flex
virtual/pkgconfig
sys-devel/crossdev
dev-embedded/u-boot-tools
"
src_prepare() {
default
sed -i 's:\bpkg-config\b:${PKG_CONFIG}:g' \
scripts/kconfig/{g,m,n,q}conf-cfg.sh \
scripts/kconfig/Makefile \
tools/Makefile || die
#Apply PinePhone Pro patches
eapply "${FILESDIR}"/1001-Correct-boot-order-to-be-USB-SD-eMMC.patch
eapply "${FILESDIR}"/1002-rockchip-Add-initial-support-for-the-PinePhone-Pro.patch
#eapply "${FILESDIR}"/1003-Configure-USB-power-settings-for-PinePhone-Pro.patch
eapply "${FILESDIR}"/1004-mtd-spi-nor-ids-Add-GigaDevice-GD25LQ128E-entry.patch
eapply "${FILESDIR}"/1005-Reconfigure-GPIO4_D3-as-input-on-PinePhone-Pro.patch
eapply "${FILESDIR}"/2001-mmc-sdhci-allow-disabling-sdma-in-spl.patch
eapply "${FILESDIR}"/3001-pinephone-pro-Remove-cargo-culted-iodomain-config.patch
eapply "${FILESDIR}"/3002-pine64-pinephonePro-SPI-support.patch
}
src_configure() {
tc-export AR BUILD_CC CC PKG_CONFIG
}
src_compile() {
unset CFLAGS CXXFLAGS CPPFLAGS LDFLAGS
cd ${WORKDIR}/trusted-firmware-a-${FIRMWAREVERSION}
emake "${myemakeargs[@]}" PLAT=rk3399
cp build/rk3399/release/bl31/bl31.elf ${S}
cd ${S}
# Unset a few KBUILD variables. Bug #540476
unset KBUILD_OUTPUT KBUILD_SRC
emake "${myemakeargs[@]}" pinephone-pro-rk3399_defconfig
local myemakeargs=(
V=1
AR="${AR}"
CC="${CC}"
HOSTCC="${BUILD_CC}"
HOSTCFLAGS="${BUILD_CFLAGS} ${BUILD_CPPFLAGS}"' $(HOSTCPPFLAGS)'
HOSTLDFLAGS="${BUILD_LDFLAGS}"
)
echo "CONFIG_IDENT_STRING='Gentoo Linux'" >> .config
echo "CONFIG_BOOTDELAY'='0'" >> .config
echo "CONFIG_SPL_DM_SEQ_ALIAS='y'" >> .config
echo "CONFIG_SF_DEFAULT_BUS='1'" >> .config
echo "CONFIG_SPL_MMC_SDHCI_SDMA'='n'" >> .config
emake "${myemakeargs[@]}" EXTRAVERSION=-${PKGREL}
}
src_test() { :; }
src_install() {
insinto /boot/
doins ${S}/u-boot.itb
doins ${S}/idbloader.img
doins ${FILESDIR}/boot.txt
dobin ${FILESDIR}/ppp-uboot-mkscr
}
pkg_postinst() {
einfo "In order to get the U-Boot to work you will need a crosscompiler for arm-none-eabi you can do this by running: crossdev --target arm-none-eabi (if not done allready) and then re-emerge this packages"
einfo "This U-Boot is only to be used for the PinePhone Pro."
einfo "Edit the /boot/boot.txt file with your uuid's and then run ppp-uboot-mkscr"
einfo "After compiling a new Gentoo kernel, copy the resulting Image from /usr/src/linux/arch/arm64/boot/Image to the boot partition (replacing the existing Image)."
einfo "New version of U-Boot firmware can be flashed to your microSD card or eMMc module."
einfo "You can do that by running:"
einfo "# dd if=/boot/idbloader.img of=/dev/mmcblkX seek=64 conv=notrunc,fsync"
einfo "# dd if=/boot/u-boot.itb of=/dev/mmcblkX seek=16384 conv=notrunc,fsync"
einfo "Due to the Boot Priority for the PPP it is HIGHLY recommended to not put U-Boot on the eMMc because there is no easy way to recover is something went wrong."
}